[PATCH v5 0/3] Enable Zicbom in usermode

[Alexandre Ghiti]

Hi Yunhui,

On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui <cuiyunhui at bytedance.com> wrote:
>
> v1/v2:
> There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode,
> which mainly removes the enabling of cbo.inval in user mode.
>
> v3:
> Add the functionality of Expose Zicbom and selftests for Zicbom.
>
> v4:
> Modify the order of macros, The test_no_cbo_inval function is added
> separately.
>
> v5:
> 1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst
> 2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL"
>
> Yunhui Cui (3):
>   RISC-V: Enable cbo.clean/flush in usermode
>   RISC-V: hwprobe: Expose Zicbom extension and its block size
>   RISC-V: selftests: Add TEST_ZICBOM into CBO tests
>
>  Documentation/arch/riscv/hwprobe.rst        |  6 ++
>  arch/riscv/include/asm/hwprobe.h            |  2 +-
>  arch/riscv/include/uapi/asm/hwprobe.h       |  2 +
>  arch/riscv/kernel/cpufeature.c              |  8 +++
>  arch/riscv/kernel/sys_hwprobe.c             |  6 ++
>  tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++----
>  6 files changed, 78 insertions(+), 12 deletions(-)
>
> --
> 2.39.2
>

So a v6 needs to be sent with:

- the fix for hwprobe_ext0_has() reported by kernel test robot
- a rebase on top of 6.14 since patch 2 will conflict with
RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0

Do you think you can do that soon so that it gets merged in 6.15? The
patchset received a lot of RB so it would be too bad to miss this
release.

Thanks,

Alex