[PATCH v4 08/21] RISC-V: Add Sscfg extension CSR definition

[Clément Léger]

On 06/02/2025 08:23, Atish Patra wrote:
> From: Kaiwen Xue <kaiwenx at rivosinc.com>
> 
> This adds the scountinhibit CSR definition and S-mode accessible hpmevent
> bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop
> counters directly from S-mode without invoking SBI calls to M-mode. It is
> also used to figure out the counters delegated to S-mode by the M-mode as
> well.
> 
> Signed-off-by: Kaiwen Xue <kaiwenx at rivosinc.com>
> ---
>  arch/riscv/include/asm/csr.h | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 2ad2d492e6b4..42b7f4f7ec0f 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -224,6 +224,31 @@
>  #define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
>  #define SMSTATEEN0_SSTATEEN0_SHIFT	63
>  #define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
> +/* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */
> +#ifdef CONFIG_64BIT
> +#define HPMEVENT_OF			(_UL(1) << 63)
> +#define HPMEVENT_MINH			(_UL(1) << 62)
> +#define HPMEVENT_SINH			(_UL(1) << 61)
> +#define HPMEVENT_UINH			(_UL(1) << 60)
> +#define HPMEVENT_VSINH			(_UL(1) << 59)
> +#define HPMEVENT_VUINH			(_UL(1) << 58)
> +#else
> +#define HPMEVENTH_OF			(_ULL(1) << 31)
> +#define HPMEVENTH_MINH			(_ULL(1) << 30)
> +#define HPMEVENTH_SINH			(_ULL(1) << 29)
> +#define HPMEVENTH_UINH			(_ULL(1) << 28)
> +#define HPMEVENTH_VSINH			(_ULL(1) << 27)
> +#define HPMEVENTH_VUINH			(_ULL(1) << 26)

Hi Atish,

Could you use BIT_UL/BIT_ULL() ? With that fixed,

Reviewed-by: Clément Léger <cleger at rivosinc.com>

Thanks,

Clément

> +
> +#define HPMEVENT_OF			(HPMEVENTH_OF << 32)
> +#define HPMEVENT_MINH			(HPMEVENTH_MINH << 32)
> +#define HPMEVENT_SINH			(HPMEVENTH_SINH << 32)
> +#define HPMEVENT_UINH			(HPMEVENTH_UINH << 32)
> +#define HPMEVENT_VSINH			(HPMEVENTH_VSINH << 32)
> +#define HPMEVENT_VUINH			(HPMEVENTH_VUINH << 32)
> +#endif
> +
> +#define SISELECT_SSCCFG_BASE		0x40
>  
>  /* mseccfg bits */
>  #define MSECCFG_PMM			ENVCFG_PMM
> @@ -305,6 +330,7 @@
>  #define CSR_SCOUNTEREN		0x106
>  #define CSR_SENVCFG		0x10a
>  #define CSR_SSTATEEN0		0x10c
> +#define CSR_SCOUNTINHIBIT	0x120
>  #define CSR_SSCRATCH		0x140
>  #define CSR_SEPC		0x141
>  #define CSR_SCAUSE		0x142
>