[PATCH v2] clk: thead: Fix TH1520 emmc and shdci clock rate

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Stephen Boyd <sboyd at kernel.org>:

On Tue, 10 Dec 2024 11:30:27 +0300 you wrote:
> From: Maksim Kiselev <bigunclemax at gmail.com>
> 
> In accordance with LicheePi 4A BSP the clock that comes to emmc/sdhci
> is 198Mhz which is got through frequency division of source clock
> VIDEO PLL by 4 [1].
> 
> But now the AP_SUBSYS driver sets the CLK EMMC SDIO to the same
> frequency as the VIDEO PLL, equal to 792 MHz. This causes emmc/sdhci
> to work 4 times slower.
> 
> [...]

Here is the summary with links:
  - [v2] clk: thead: Fix TH1520 emmc and shdci clock rate
    https://git.kernel.org/riscv/c/f4bf0b909a6b

You are awesome, thank you!
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