[PATCH v4 1/6] clk: correct clk_div_mask() return value for width == 32

[David Laight]

On Wed, 31 Dec 2025 14:40:05 +0800
Junhui Liu <junhui.liu at pigmoral.tech> wrote:

> The macro clk_div_mask() currently wraps to zero when width is 32 due to
> 1 << 32 being undefined behavior. This leads to incorrect mask generation
> and prevents correct retrieval of register field values for 32-bit-wide
> dividers.
> 
> Although it is unlikely to exhaust all U32_MAX div, some clock IPs may rely
> on a 32-bit val entry in their div_table to match a div, so providing a
> full 32-bit mask is necessary.
> 
> Fix this by casting 1 to long, ensuring proper behavior for valid widths up
> to 32.
> 
> Reviewed-by: Troy Mitchell <troy.mitchell at linux.spacemit.com>
> Reviewed-by: Brian Masney <bmasney at redhat.com>
> Signed-off-by: Junhui Liu <junhui.liu at pigmoral.tech>
> ---
>  include/linux/clk-provider.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 630705a47129..a651ccaf1b44 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -720,7 +720,7 @@ struct clk_divider {
>  	spinlock_t	*lock;
>  };
>  
> -#define clk_div_mask(width)	((1 << (width)) - 1)
> +#define clk_div_mask(width)	((1L << (width)) - 1)

That makes no difference on 32bit architectures.
I also suspect you need to ensure the value is 'unsigned int'.
If you can guarantee that width isn't zero (probably true), then:
#define clk_div_mask(width) ((2u << (width) - 1) - 1)
should have the desired value for widths 1..32.
It probably adds an extra instruction.
(OTOH so does passing width as 'u8'.)

	David


>  #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
>  
>  #define CLK_DIVIDER_ONE_BASED		BIT(0)
>