[PATCH v2 09/13] dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl

[Guodong Xu]

Hi, Alex

On Sat, Dec 27, 2025 at 5:28 AM Alex Elder <elder at riscstar.com> wrote:
>
> On 12/22/25 7:04 AM, Guodong Xu wrote:
> > Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala,
> > Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles
> > Version 1.0 (commit b1d806605f87 "Updated to ratified state.").
> >
> > They are introduced as new extension names for existing features and
> > regulate implementation details for RISC-V Profile compliance. According
> > to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their
> > requirement status are:
> >
> >   - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64
> >   - Sscounterenw: Mandatory in RVA22S64, RVA23S64
> >   - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64
> >   - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64
> >   - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64
>
> Again, I did not verify your statements about where these are
> optional and mandatory, but I assume they're correct.

Thanks for the review.

As mentioned in my response to patch 8, the requirement status for these
extensions is clearly defined in the RISC-V Profiles specification(s) which
I mentioned above.

I have verified these details against the official document to ensure
accuracy.

The extension descriptions are included in the commit message to provide
necessary background information.

>
> > Signed-off-by: Guodong Xu <guodong at riscstar.com>
> > ---
> > v2: New patch.
> > ---
> >   .../devicetree/bindings/riscv/extensions.yaml      | 32 ++++++++++++++++++++++
> >   1 file changed, 32 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index a6b9d7e3edf86ecfb117ba72e295ef097bdc9831..ed7a88c0ab3b7dc7ad4a4d2fd300d6fb33ef050c 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -160,12 +160,26 @@ properties:
> >               behavioural changes to interrupts as frozen at commit ccbddab
> >               ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
> >
> > +        - const: ssccptr
> > +          description: |
> > +            The standard Ssccptr extension for main memory (cacheability and
> > +            coherence) hardware page-table reads, as ratified in RISC-V
> > +            Profiles Version 1.0, with commit b1d806605f87 ("Updated to
> > +            ratified state.")
> > +
> >           - const: sscofpmf
> >             description: |
> >               The standard Sscofpmf supervisor-level extension for count overflow
> >               and mode-based filtering as ratified at commit 01d1df0 ("Add ability
> >               to manually trigger workflow. (#2)") of riscv-count-overflow.
> >
> > +        - const: sscounterenw
> > +          description: |
> > +            The standard Sscounterenw extension for support writable enables
> > +            in scounteren for any supported counter, as ratified in RISC-V

Here, I used the abbreviated version. See below.

> > +            Profiles Version 1.0, with commit b1d806605f87 ("Updated to
> > +            ratified state.")
>
> Maybe you should just copy the text from the RVA23 specification
> for all of these.  So something like:
>
>    For any hpmcounter that is not read-only zero, the corresponding
>    bit in scounteren must be writable.  This was ratified in the
>    RISC-V Profiles specification version 1.0, with commit ...
>

As you noticed, the RVA23 Profile v1.0 provides two versions of explanation
for Sscounterenw:
"Sscounterenw: For any hpmcounter that is not read-only zero, the corresponding
bit in scounteren must be writable"
"Sscounterenw: Support writeable enables for any supported counter"

BR,
Guodong Xu

> > +
> >           - const: ssnpm
> >             description: |
> >               The standard Ssnpm extension for next-mode pointer masking as
> > @@ -178,6 +192,24 @@ properties:
> >               ratified at commit 3f9ed34 ("Add ability to manually trigger
> >               workflow. (#2)") of riscv-time-compare.
> >
> > +        - const: sstvala
> > +          description: |
> > +            The standard Sstvala extension for stval provides all needed values
> > +            as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
> > +            ("Updated to ratified state.")
>
> Or alternative to the full text in the spec, you could copy over
> the abbreviated description listed in the glossary at the end
> instead.  Something like:
>
>    stval provides all needed values.  This was ratified in...
>
>                                         -Alex
>
> > +
> > +        - const: sstvecd
> > +          description: |
> > +            The standard Sstvecd extension for stvec supports Direct mode as
> > +            ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
> > +            ("Updated to ratified state.")
> > +
> > +        - const: ssu64xl
> > +          description: |
> > +            The standard Ssu64xl extension for UXLEN=64 must be supported, as
> > +            ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
> > +            ("Updated to ratified state.")
> > +
> >           - const: svade
> >             description: |
> >               The standard Svade supervisor-level extension for SW-managed PTE A/D
> >
>