[PATCH 1/8] dt-bindings: riscv: add SpacemiT X100 CPU compatible

[Guodong Xu]

On Tue, Dec 16, 2025 at 11:33 PM Krzysztof Kozlowski <krzk at kernel.org> wrote:
>
> On 16/12/2025 14:32, Guodong Xu wrote:
> > Add compatible string for the SpacemiT X100 (RVA23 compliant) core.
> >
> > Link: https://www.spacemit.com/en/spacemit-x100-core/
> >
> > Signed-off-by: Guodong Xu <guodong at riscstar.com>
> > ---
> >  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index d733c0bd534fb63ed7c0eada97c42832431f1fc1..cce87092dc7749f49066154d9a256af6c7b6c19f 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -62,6 +62,7 @@ properties:
> >                - sifive,u74
> >                - sifive,u74-mc
> >                - spacemit,x60
> > +              - spacemit,x100
>
>
> Two reviews of this one-liner but no one pointed out that sorting is
> broken... What is being exactly reviewed in this one-liner?

Thanks Krzysztof. I will fix that, put x100 before x60.

BR,
Guodong

>
> Best regards,
> Krzysztof