[PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

[Anand Moon]

Hi Hal,

On Fri, 5 Dec 2025 at 13:11, Hal Feng <hal.feng at starfivetech.com> wrote:
>
> > On 05.12.25 01:05, Anand Moon wrote:
> > Hi Hal,
> >
> > On Tue, 25 Nov 2025 at 13:27, Hal Feng <hal.feng at starfivetech.com> wrote:
> > >
> > > Add a common board dtsi for use by VisionFive 2 Lite and VisionFive 2
> > > Lite eMMC.
> > >
> > > Acked-by: Emil Renner Berthing <emil.renner.berthing at canonical.com>
> > > Tested-by: Matthias Brugger <mbrugger at suse.com>
> > > Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
> > > ---
> > >  .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
> > >  1 file changed, 161 insertions(+)
> > >  create mode 100644
> > > arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > >
> > > diff --git
> > > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > > new file mode 100644
> > > index 000000000000..f8797a666dbf
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.d
> > > +++ tsi
> > > @@ -0,0 +1,161 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> > > + * Copyright (C) 2025 Hal Feng <hal.feng at starfivetech.com>  */
> > > +
> > > +/dts-v1/;
> > > +#include "jh7110-common.dtsi"
> > > +
> > > +/ {
> > > +       vcc_3v3_pcie: regulator-vcc-3v3-pcie {
> > > +               compatible = "regulator-fixed";
> > > +               enable-active-high;
> > > +               gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
> > > +               regulator-name = "vcc_3v3_pcie";
> > > +               regulator-min-microvolt = <3300000>;
> > > +               regulator-max-microvolt = <3300000>;
> > > +       };
> > > +};
> >
> > The vcc_3v3_pcie regulator node is common to all JH7110 development
> > boards.
> > and it is enabled through the PWREN_H signal (PCIE0_PWREN_H_GPIO32).
> >
> > VisionFive 2 Product Design Schematics below [1] https://doc-
> > en.rvspace.org/VisionFive2/PDF/SCH_RV002_V1.2A_20221216.pdf
> >
> > Mars_Hardware_Schematics
> > [2] https://github.com/milkv-mars/mars-
> > files/blob/main/Mars_Hardware_Schematics/Milk-
> > V_Mars_SCH_V1.21_2024-0510.pdf
>
> No, GPIO32 is connected to the WAKE pin, it is not used to control the PCIe slot power.
>
Ok, GPIO32 is used for pcie0 (PCIE0_PWREN_H_GPIO32)
Only PCIE0 supports power for the 4-port USB ports.

As per VisionFive 2 Single Board Computer Quick Start Guide
USB30 4 × USB 3.0 ports (multiplexed with a PCIe 2.0 1x lane).

> Best regards,
> Hal

Thanks
-Anand