[PATCH v5 0/6] Basic device tree support for ESWIN EIC7700 RISC-V SoC

[Pinkesh Vaghela]

Hello Arnd,

Can you please consider this patch series for RISC-V/Eswin EIC7700 SOC.

Regards,
Pinkesh

On Mon, Aug 25, 2025 at 06:54 PM, Pinkesh Vaghela wrote:
> Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
> P550 CPU cluster and the first development board that uses it, the SiFive
> HiFive Premier P550.
>
> This patch series adds initial device tree and also adds ESWIN architecture
> support.
>
> Boot-tested using intiramfs with Linux v6.17-rc3 on HiFive Premier
> P550 board using U-Boot 2024.01 and OpenSBI 1.4.
>
> Changes in v5:
> - Rebased the patches to kernel v6.17-rc3
> - Drop "dt-bindings: vendor-prefixes: add eswin" patch (Patch #3 in v4)
>   as it is already applied by Rob Herring [1].
> - Link to v4:
> https://lore.k/
> ernel.org%2Flkml%2F20250616112316.3833343-1-
> pinkesh.vaghela%40einfochips.com%2F&data=05%7C02%7Cpinkesh.vaghela%
> 40einfochips.com%7Ca7a3db36d4f8414d95dd08dde3dab8ef%7C0beb0c359c
> bb4feb99e5589e415c7944%7C1%7C0%7C638917250735611269%7CUnknown
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> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=
> eqrfYDxwbfOccXZ7im7%2BBS5ZWaLZZML0jfMac5yRRiA%3D&reserved=0
>
> [1]:
> https://git.ker/
> nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fnext%2Flinux-
> next.git%2Fcommit%2F%3Fh%3Dnext-
> 20250825%26id%3Dac29e4487aa20a21b7c3facbd1f14f5093835dc9&data=05
> %7C02%7Cpinkesh.vaghela%40einfochips.com%7Ca7a3db36d4f8414d95dd08
> dde3dab8ef%7C0beb0c359cbb4feb99e5589e415c7944%7C1%7C0%7C638917
> 250735660956%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydW
> UsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%
> 3D%7C0%7C%7C%7C&sdata=5CsQwP5HjO0zRAL5CPMJvkpGom5W6FiBe%2B
> GyzR1F1XU%3D&reserved=0
>
> Changes in v4:
> - Rebased the patches to kernel v6.16-rc1
> - Drop patches that are already merged
> - Added "Acked-by" tag of "Min Lin" for Patch 4
> - Corrected the commit message of Patch 7 (Patch #10 in v3)
> - Added "Tested-by" tag of "Ariel D'Alessandro" for Patch 7
> - Link to v3:
> https://lore.k/
> ernel.org%2Flkml%2F20250410152519.1358964-1-
> pinkesh.vaghela%40einfochips.com%2F&data=05%7C02%7Cpinkesh.vaghela%
> 40einfochips.com%7Ca7a3db36d4f8414d95dd08dde3dab8ef%7C0beb0c359c
> bb4feb99e5589e415c7944%7C1%7C0%7C638917250735680365%7CUnknown
> %7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAi
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=
> FgYbanGvuw2gw1jpzSbG3KciYPXlasos0sPCVXf31fQ%3D&reserved=0
>
> Changes in v3:
> - Rebased the patches to kernel 6.15.0-rc1
> - Added "Reviewed-by" tag of "Rob Herring" for Patch 4
> - Updated MAINTAINERS file
>   - Add GIT tree URL
> - Updated DTSI file
>   - Added "dma-noncoherent" property to soc node
>   - Updated GPIO node labels in DTSI file
> - Link to v2:
> https://lore.k/
> ernel.org%2Flkml%2F20250320105449.2094192-1-
> pinkesh.vaghela%40einfochips.com%2F&data=05%7C02%7Cpinkesh.vaghela%
> 40einfochips.com%7Ca7a3db36d4f8414d95dd08dde3dab8ef%7C0beb0c359c
> bb4feb99e5589e415c7944%7C1%7C0%7C638917250735700104%7CUnknown
> %7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAi
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=
> kvHq5Hf30zj9%2B%2BBQ6aoat0i7RL14roD8%2B2bCYJRKiR4%3D&reserved=0
>
> Changes in v2:
> - Added "Acked-by" tag of "Conor Dooley" for Patches 1, 2, 3, 7 and 8
> - Added "Reviewed-by" tag of "Matthias Brugger" for Patch 4
> - Updated MAINTAINERS file
>   - Add the path for the eswin binding file
> - Updated sifive,ccache0.yaml
>   - Add restrictions for "cache-size" property based on the
>     compatible string
> - Link to v1:
> https://lore.k/
> ernel.org%2Flkml%2F20250311073432.4068512-1-
> pinkesh.vaghela%40einfochips.com%2F&data=05%7C02%7Cpinkesh.vaghela%
> 40einfochips.com%7Ca7a3db36d4f8414d95dd08dde3dab8ef%7C0beb0c359c
> bb4feb99e5589e415c7944%7C1%7C0%7C638917250735720668%7CUnknown
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> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=
> xy7c5b96WT208HoJvQ03nZR14ZZrsfQaqfpZNdecSXk%3D&reserved=0
>
> Darshan Prajapati (2):
>   dt-bindings: riscv: Add SiFive P550 CPU compatible
>   dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC
>
> Min Lin (2):
>   riscv: dts: add initial support for EIC7700 SoC
>   riscv: dts: eswin: add HiFive Premier P550 board device tree
>
> Pinkesh Vaghela (1):
>   riscv: Add Kconfig option for ESWIN platforms
>
> Pritesh Patel (1):
>   dt-bindings: riscv: Add SiFive HiFive Premier P550 board
>
>  .../sifive,plic-1.0.0.yaml                    |   1 +
>  .../devicetree/bindings/riscv/cpus.yaml       |   1 +
>  .../devicetree/bindings/riscv/eswin.yaml      |  29 ++
>  MAINTAINERS                                   |   9 +
>  arch/riscv/Kconfig.socs                       |   6 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/eswin/Makefile            |   2 +
>  .../dts/eswin/eic7700-hifive-premier-p550.dts |  29 ++
>  arch/riscv/boot/dts/eswin/eic7700.dtsi        | 345 ++++++++++++++++++
>  9 files changed, 423 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/eswin.yaml
>  create mode 100644 arch/riscv/boot/dts/eswin/Makefile
>  create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-
> p550.dts
>  create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi
>
> --
> 2.25.1