RISC-V big-endian support

[Ben Dooks]

This is a new series for `experimental` support for big-endian RISC-V
operation. This has now been tested on both QEMU and a Codethink built
CVA6 FPGA as well as being joined by MIPS and their I8500.

Since MIPS will be shipping systems with big-endian support and the
work we have done with QEMU, we feel that there there is now a good
case for this support to be upstreamed.

The support is currently gated by CONFIG_EXPRIMENTAL until we get more
testing through, and removes CONFIG_VECTOR and the 32bit compatibiltiy
as this has not been tested and needs work.

The KVM support does include an interface to allow access to the HSTATUS
to allow running KVM with different endian-ness to the host (which has
been through a very quick test). We'll push kvmtool pathches once this
has been reviewed.

We have a big-endian buildroot with ucblic on our project page, and will
be working to send updates to buildroot, uclibc, u-boot and qemu with
more work being done by MIPS which will include glibc, clang/llvm, etc.

Project page: https://gitlab.com/CodethinkLabs/riscv_bigendian
MIPS I8500: https://mips.com/products/hardware/i8500/
Kernel branch: https://gitlab.com/CodethinkLabs/linux-kernel/-/commits/bjdooks/dev_v617_rc2