[PATCH] sifive: fix using wrong load type

[Troy Mitchell]

On Mon, Aug 18, 2025 at 02:13:36PM +0800, Jimmy Ho wrote:
> thread_info.cpu field is 32 bits wide,
> but is accessed using an XLEN-bit load, which might be 64bit load, fix it
> 
> Signed-off-by: Jimmy Ho <jimmy.ho at sifive.com>
> ---
>  arch/riscv/kernel/entry.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 3a0ec6fd5956..ed493cd3dc35 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -46,7 +46,7 @@
>  	 * a0 = &new_vmalloc[BIT_WORD(cpu)]
>  	 * a1 = BIT_MASK(cpu)
>  	 */
> -	REG_L 	a2, TASK_TI_CPU(tp)
> +	lw a2, TASK_TI_CPU(tp)
We better add a comment to explain why use lw instead of REG_L.

                - Troy
>  	/*
>  	 * Compute the new_vmalloc element position:
>  	 * (cpu / 64) * 8 = (cpu >> 6) << 3
> -- 
> 2.39.3
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv