[PATCH v2 2/3] riscv: dts: starfive: jh7110: add DMC memory controller

[Hal Feng]

> On 15.08.25 15:37, E Shattow wrote:
> Add JH7110 SoC DDR external memory controller.
> 
> Signed-off-by: E Shattow <e at freeshell.de>
> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 0ba74ef04679..14df3d062a45 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -372,6 +372,18 @@ ccache: cache-controller at 2010000 {
>  			cache-unified;
>  		};
> 
> +		memory-controller at 15700000 {
> +			compatible = "starfive,jh7110-dmc";
> +			reg = <0x0 0x15700000 0x0 0x10000>,
> +			      <0x0 0x13000000 0x0 0x10000>;
> +			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> +			clock-names = "pll1_out";
> +			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> +				 <&syscrg JH7110_SYSRST_DDR_OSC>,
> +				 <&syscrg JH7110_SYSRST_DDR_APB>;
> +			reset-names = "axi", "osc", "apb";
> +		};
> +
>  		plic: interrupt-controller at c000000 {
>  			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
>  			reg = <0x0 0xc000000 0x0 0x4000000>;

Nodes are sorted by reg address. So please place memory-controller at 15700000
between watchdog at 13070000 and crypto at 16000000. Thanks.

Best regards,
Hal