[PATCH v4 1/3] clock: eswin: Documentation for eic7700 SoC

[Krzysztof Kozlowski]

On 15/08/2025 11:36, dongxuyang at eswincomputing.com wrote:
> From: Xuyang Dong <dongxuyang at eswincomputing.com>
> 
> Add device tree binding documentation for the ESWIN eic7700
> clock controller module.
> 
> Signed-off-by: Yifeng Huang <huangyifeng at eswincomputing.com>
> Signed-off-by: Xuyang Dong <dongxuyang at eswincomputing.com>
> ---
>  .../bindings/clock/eswin,eic7700-clock.yaml   | 381 ++++++++++++++++++
>  1 file changed, 381 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
> new file mode 100644
> index 000000000000..45e70ebc08e6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
> @@ -0,0 +1,381 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Eswin EIC7700 SoC clock controller
> +
> +maintainers:
> +  - Yifeng Huang <huangyifeng at eswincomputing.com>
> +  - Xuyang Dong <dongxuyang at eswincomputing.com>
> +
> +description:
> +  The clock controller generates and supplies clock to all the modules
> +  for eic7700 SoC.
> +
> +properties:
> +  compatible:
> +    const: eswin,eic7700-clock
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 0
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 0
> +
> +required:

Incorrectly placed. required is after all properties.

> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +  - '#address-cells'
> +  - '#size-cells'
> +
> +patternProperties:
> +  "^fixed-rate.*":
> +    type: object
> +    $ref: /schemas/clock/fixed-clock.yaml#

No, you do not get node per clock.

> +
> +  ".*pll@[a-f0-9]+$":
> +    type: object
> +
> +    properties:
> +      compatible:
> +        const: eswin,pll-clock


Nothing explains in the changelog why this appeared. Drop all these
nodes and fake or redundant compatibles.


> +
> +      reg:
> +        items:
> +          - description: PLL's config 0 register
> +          - description: PLL's config 1 register
> +          - description: PLL's config 2 register
> +          - description: PLL's status register
> +
> +      '#clock-cells':
> +        const: 0
> +
> +      clock-output-names:
> +        maxItems: 1
> +
> +      enable-shift:
> +        description: Bit shift of the enable register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      enable-width:
> +        description: Width of the enable register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      refdiv-shift:
> +        description: Bit shift of the reference divider register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      refdiv-width:
> +        description: Width of the reference divider register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      fbdiv-shift:
> +        description: Bit shift of the feedback divider register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      fbdiv-width:
> +        description: Width of the feedback divider register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      frac-shift:
> +        description: Bit shift of the fractional divider register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      frac-width:
> +        description: Width of the fractional divider register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      postdiv1-shift:
> +        description: Bit shift of the post divider 1 register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      postdiv1-width:
> +        description: Width of the post divider 1 register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      postdiv2-shift:
> +        description: Bit shift of the post divider 2 register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      postdiv2-width:
> +        description: Width of the post divider 2 register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        maximum: 31
> +
> +      lock-shift:
> +        description: Bit shift of the lock register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +      lock-width:
> +        description: Width of the lock register.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        minimum: 0
> +        maximum: 31
> +
> +    required:
> +      - compatible
> +      - reg
> +      - '#clock-cells'
> +      - clock-output-names
> +      - enable-shift
> +      - enable-width
> +      - refdiv-shift
> +      - refdiv-width
> +      - fbdiv-shift
> +      - fbdiv-width
> +      - frac-shift
> +      - frac-width
> +      - postdiv1-shift
> +      - postdiv1-width
> +      - postdiv2-shift
> +      - postdiv2-width
> +      - lock-shift
> +      - lock-width
> +
> +    additionalProperties: false
> +
> +  ".*mux@[a-f0-9]+$":
> +    type: object

NAK, but anyway explain in the changelog WHY you did this...


Best regards,
Krzysztof