[PATCH v6 1/5] riscv: add SBI SSE extension definitions

[Alexandre Ghiti]

Hi Clément,

On 8/8/25 17:38, Clément Léger wrote:
> Add needed definitions for SBI Supervisor Software Events extension [1].
> This extension enables the SBI to inject events into supervisor software
> much like ARM SDEI.
>
> [1] https://lists.riscv.org/g/tech-prs/message/515
>
> Signed-off-by: Clément Léger <cleger at rivosinc.com>
> ---
>   arch/riscv/include/asm/sbi.h | 61 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 341e74238aa0..e4993fb664d2 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -36,6 +36,7 @@ enum sbi_ext_id {
>   	SBI_EXT_STA = 0x535441,
>   	SBI_EXT_NACL = 0x4E41434C,
>   	SBI_EXT_FWFT = 0x46574654,
> +	SBI_EXT_SSE = 0x535345,
>   
>   	/* Experimentals extensions must lie within this range */
>   	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
> @@ -430,6 +431,66 @@ enum sbi_fwft_feature_t {
>   
>   #define SBI_FWFT_SET_FLAG_LOCK			BIT(0)
>   
> +enum sbi_ext_sse_fid {
> +	SBI_SSE_EVENT_ATTR_READ = 0,
> +	SBI_SSE_EVENT_ATTR_WRITE,
> +	SBI_SSE_EVENT_REGISTER,
> +	SBI_SSE_EVENT_UNREGISTER,
> +	SBI_SSE_EVENT_ENABLE,
> +	SBI_SSE_EVENT_DISABLE,
> +	SBI_SSE_EVENT_COMPLETE,
> +	SBI_SSE_EVENT_SIGNAL,


Nit but in the specification this event is referred as "inject" instead 
of "signal", any reason to change that naming?


> +	SBI_SSE_EVENT_HART_UNMASK,
> +	SBI_SSE_EVENT_HART_MASK,
> +};
> +
> +enum sbi_sse_state {
> +	SBI_SSE_STATE_UNUSED     = 0,
> +	SBI_SSE_STATE_REGISTERED = 1,
> +	SBI_SSE_STATE_ENABLED    = 2,
> +	SBI_SSE_STATE_RUNNING    = 3,
> +};
> +
> +/* SBI SSE Event Attributes. */
> +enum sbi_sse_attr_id {
> +	SBI_SSE_ATTR_STATUS		= 0x00000000,
> +	SBI_SSE_ATTR_PRIO		= 0x00000001,
> +	SBI_SSE_ATTR_CONFIG		= 0x00000002,
> +	SBI_SSE_ATTR_PREFERRED_HART	= 0x00000003,
> +	SBI_SSE_ATTR_ENTRY_PC		= 0x00000004,
> +	SBI_SSE_ATTR_ENTRY_ARG		= 0x00000005,
> +	SBI_SSE_ATTR_INTERRUPTED_SEPC	= 0x00000006,
> +	SBI_SSE_ATTR_INTERRUPTED_FLAGS	= 0x00000007,
> +	SBI_SSE_ATTR_INTERRUPTED_A6	= 0x00000008,
> +	SBI_SSE_ATTR_INTERRUPTED_A7	= 0x00000009,
> +
> +	SBI_SSE_ATTR_MAX		= 0x0000000A
> +};
> +
> +#define SBI_SSE_ATTR_STATUS_STATE_OFFSET	0
> +#define SBI_SSE_ATTR_STATUS_STATE_MASK		0x3
> +#define SBI_SSE_ATTR_STATUS_PENDING_OFFSET	2
> +#define SBI_SSE_ATTR_STATUS_INJECT_OFFSET	3
> +
> +#define SBI_SSE_ATTR_CONFIG_ONESHOT	BIT(0)
> +
> +#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPP	BIT(0)
> +#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SSTATUS_SPIE	BIT(1)
> +#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPV	BIT(2)
> +#define SBI_SSE_ATTR_INTERRUPTED_FLAGS_HSTATUS_SPVP	BIT(3)
> +
> +#define SBI_SSE_EVENT_LOCAL_HIGH_PRIO_RAS	0x00000000
> +#define SBI_SSE_EVENT_LOCAL_DOUBLE_TRAP		0x00000001
> +#define SBI_SSE_EVENT_GLOBAL_HIGH_PRIO_RAS	0x00008000
> +#define SBI_SSE_EVENT_LOCAL_PMU_OVERFLOW	0x00010000
> +#define SBI_SSE_EVENT_LOCAL_LOW_PRIO_RAS	0x00100000
> +#define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
> +#define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000
> +#define SBI_SSE_EVENT_GLOBAL_SOFTWARE_INJECTED	0xffff8000


And here you use "injected".


> +
> +#define SBI_SSE_EVENT_PLATFORM		BIT(14)
> +#define SBI_SSE_EVENT_GLOBAL		BIT(15)
> +
>   /* SBI spec version fields */
>   #define SBI_SPEC_VERSION_DEFAULT	0x1
>   #define SBI_SPEC_VERSION_MAJOR_SHIFT	24