[PATCH] irqchip/sifive-plic: Respect mask state when setting affinity

[Inochi Amaoto]

On Fri, Aug 08, 2025 at 06:01:39AM +0800, Inochi Amaoto wrote:
> On Thu, Aug 07, 2025 at 02:39:42PM +0200, Nam Cao wrote:
> > Inochi Amaoto <inochiama at gmail.com> writes:
> > 
> > > The plic_set_affinity always call plic_irq_enable(), which clears up
> > > the priority setting even the irq is only masked. This make the irq
> > > unmasked unexpectly.
> > >
> > > Replace the plic_irq_enable/disable() with plic_irq_toggle() to
> > > avoid changing priority setting.
> > >
> > > Suggested-by: Thomas Gleixner <tglx at linutronix.de>
> > > Signed-off-by: Inochi Amaoto <inochiama at gmail.com>
> > > ---
> > >  drivers/irqchip/irq-sifive-plic.c | 7 +++++--
> > >  1 file changed, 5 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > > index bf69a4802b71..5bf5050996da 100644
> > > --- a/drivers/irqchip/irq-sifive-plic.c
> > > +++ b/drivers/irqchip/irq-sifive-plic.c
> > > @@ -148,6 +148,7 @@ static void plic_irq_enable(struct irq_data *d)
> > >  
> > >  static void plic_irq_disable(struct irq_data *d)
> > >  {
> > > +	plic_irq_mask(d);
> > >  	plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
> > >  }
> > 
> > This part is not required for the problem you are addressing, right?
> > 
> > I do not oppose the change, I'm just curious if I miss something here.
> > 
> 
> It is true, this is added because it is needed to follow
> the disable required of the irqchip. I think it is better
> to split to a separate one.
> 

After some dig in, I found it is not very necessary to add this,
When all enable bit is clear, the PRIORIT register of irq is
not functional, so only umask the irq does not make sense. Only
calling irq_enable does enable the irq.

I prefer to add a comment to describe this behavior, instead of
adding this change in a separate patch.

Regards,
Inochi