[GIT PULL] RISC-V Patches for the 6.17 Merge Window, Part 1
Alexandre Ghiti
alex at ghiti.fr
Fri Aug 1 05:41:15 PDT 2025
The following changes since commit 89be9a83ccf1f88522317ce02f854f30d6115c41:
Linux 6.16-rc7 (2025-07-20 15:18:33 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux.git/
tags/riscv-mw1-6.17
for you to fetch changes up to 5ec6b493183c4706216347853d3446c36ed399d1:
riscv: introduce ioremap_wc() (2025-08-01 11:52:10 +0000)
----------------------------------------------------------------
riscv patches for 6.17-rc1
* Fixes
- 2 occurences of xlen-wide loads on 32bit fields which were then wrong
on 64bit
- A wrong size was passed to low-level uaccess routines in case of
misaligned accesses resulting in a regression in the glibc testsuite
* Perf improvements
- Endianness swap routines now use zbb
- Further improvement to the raid6 calculation by getting rid of a
vector load, resulting in a ~3% gain on the BPi-F3
- ioremap_wc() now uses svpbmt
* Additions
- Support ACPI BGRT table in order to display a vendor logo
- MIPS xmipsexectl extension is now supported
- We can now set satp mode from the device tree
- One errata for C9xx cores to prevent single stores to be delayed for
an indefinite duration
- Make kprobetrace available
- Make sure dependencies of zfa, zfh and zfhmin are present before
advertising them
* Tests
- raid6 userspace test can now be compiled on riscv
- misaligned access kseltest is added
- kprobe kunit test is added
* Cleanups
- A bunch of deduplication of the macros we use for manipulating
instructions
----------------------------------------------------------------
Sorry I'm very late for this PR, I clearly overestimated my ability to
work while vacationing with the kids.
As usual, no regressions were found since v6.16 on our upstream CI
(which is down for now).
CFI v19 is running the CI on top of those patches right now and will
follow this weekend.
----------------------------------------------------------------
Aleksa Paunovic (6):
dt-bindings: riscv: Add xmipsexectl ISA extension description
riscv: Add xmipsexectl as a vendor extension
riscv: Add xmipsexectl instructions
riscv: hwprobe: Add MIPS vendor extension probing
riscv: hwprobe: Document MIPS xmipsexectl vendor extension
riscv: Add tools support for xmipsexectl
Alexandre Ghiti (12):
Merge patch series "riscv: Replace __ASSEMBLY__ with
__ASSEMBLER__ in header files"
riscv: Fix typo EXRACT -> EXTRACT
riscv: Strengthen duplicate and inconsistent definition of RV_X()
riscv: Move all duplicate insn parsing macros into asm/insn.h
Merge patch series "Move duplicated instructions macros into
asm/insn.h"
Merge patch series "riscv: kprobes: Clean up instruction simulation"
Merge patch series "riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
Merge patch series "Add an optimization also raid6test for RISC-V
support"
Merge patch series "riscv: mm: Use mmu-type from FDT as SATP mode
limit"
Merge patch series "riscv: minor thread_info.cpu improvements"
Merge patch series "riscv: Add support for xmipsexectl"
Merge patch series "ACPI: support BGRT table on RISC-V"
Aurelien Jarno (1):
riscv: uaccess: fix __put_user_nocheck for unaligned accesses
Chunyan Zhang (5):
raid6: riscv: Clean up unused header file inclusion
raid6: riscv: replace one load with a move to speed up the caculation
raid6: riscv: Prevent compiler with vector support to build
already vectorized code
raid6: riscv: Allow code to be compiled in userspace
raid6: test: Add support for RISC-V
Clément Léger (2):
riscv: cpufeature: add validation for zfa, zfh and zfhmin
selftests: riscv: add misaligned access testing
Djordje Todorovic (1):
riscv: errata: Fix the PAUSE Opcode for MIPS P8700
Guo Ren (Alibaba DAMO Academy) (2):
riscv: Move vendor errata definitions to new header
riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup
Heinrich Schuchardt (2):
RISC-V: ACPI: enable parsing the BGRT table
ACPI: support BGRT table on RISC-V
Ignacio Encinas (1):
riscv: introduce asm/swab.h
Jessica Liu (1):
riscv: mmap(): use unsigned offset type in riscv_sys_mmap
Junhui Liu (2):
riscv: mm: Return intended SATP mode for noXlvl options
riscv: mm: Use mmu-type from FDT to limit SATP mode
Masahiro Yamada (1):
riscv: pi: use 'targets' instead of extra-y in Makefile
Nam Cao (12):
riscv: kprobes: Move branch_rs2_idx to insn.h
riscv: kprobes: Move branch_funct3 to insn.h
riscv: kprobes: Remove duplication of RV_EXTRACT_JTYPE_IMM
riscv: kprobes: Remove duplication of RV_EXTRACT_RS1_REG
riscv: kprobes: Remove duplication of RV_EXTRACT_BTYPE_IMM
riscv: kproves: Remove duplication of RVC_EXTRACT_JTYPE_IMM
riscv: kprobes: Remove duplication of RVC_EXTRACT_C2_RS1_REG
riscv: kprobes: Remove duplication of RVC_EXTRACT_BTYPE_IMM
riscv: kprobes: Remove duplication of RV_EXTRACT_RD_REG
riscv: kprobes: Remove duplication of RV_EXTRACT_UTYPE_IMM
riscv: kprobes: Remove duplication of RV_EXTRACT_ITYPE_IMM
riscv: Add kprobes KUnit test
Pu Lehui (1):
riscv: Enable ARCH_HAVE_NMI_SAFE_CMPXCHG
Radim Krčmář (4):
riscv: use lw when reading int cpu in new_vmalloc_check
riscv: use lw when reading int cpu in asm_per_cpu
riscv: use TASK_TI_CPU instead of TASK_TI_CPU_NUM
riscv: pack rv64 thread_info better
Thomas Huth (2):
riscv: Replace __ASSEMBLY__ with __ASSEMBLER__ in uapi headers
riscv: Replace __ASSEMBLY__ with __ASSEMBLER__ in non-uapi headers
Yunhui Cui (1):
riscv: introduce ioremap_wc()
Documentation/arch/riscv/hwprobe.rst | 9 ++
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++
arch/riscv/Kconfig | 1 +
arch/riscv/Kconfig.errata | 40 ++++++++
arch/riscv/Kconfig.vendor | 13 +++
arch/riscv/errata/Makefile | 1 +
arch/riscv/errata/mips/Makefile | 5 +
arch/riscv/errata/mips/errata.c | 67 ++++++++++++
arch/riscv/errata/thead/errata.c | 20 ++++
arch/riscv/include/asm/alternative-macros.h | 12 +--
arch/riscv/include/asm/alternative.h | 5 +-
arch/riscv/include/asm/asm-extable.h | 6 +-
arch/riscv/include/asm/asm.h | 12 +--
arch/riscv/include/asm/assembler.h | 2 +-
arch/riscv/include/asm/barrier.h | 4 +-
arch/riscv/include/asm/cache.h | 4 +-
arch/riscv/include/asm/cmpxchg.h | 3 +-
arch/riscv/include/asm/cpu_ops_sbi.h | 2 +-
arch/riscv/include/asm/csr.h | 4 +-
arch/riscv/include/asm/current.h | 4 +-
arch/riscv/include/asm/errata_list.h | 38 +++----
arch/riscv/include/asm/errata_list_vendors.h | 30 ++++++
arch/riscv/include/asm/ftrace.h | 6 +-
arch/riscv/include/asm/gpr-num.h | 6 +-
arch/riscv/include/asm/hwprobe.h | 3 +-
arch/riscv/include/asm/image.h | 4 +-
arch/riscv/include/asm/insn-def.h | 8 +-
arch/riscv/include/asm/insn.h | 215
+++++++++++++++++++++++++++++++++++----
arch/riscv/include/asm/io.h | 4 +
arch/riscv/include/asm/jump_label.h | 4 +-
arch/riscv/include/asm/kasan.h | 2 +-
arch/riscv/include/asm/kgdb.h | 4 +-
arch/riscv/include/asm/mmu.h | 4 +-
arch/riscv/include/asm/page.h | 4 +-
arch/riscv/include/asm/pgtable.h | 5 +-
arch/riscv/include/asm/processor.h | 4 +-
arch/riscv/include/asm/ptrace.h | 4 +-
arch/riscv/include/asm/rwonce.h | 34 +++++++
arch/riscv/include/asm/scs.h | 4 +-
arch/riscv/include/asm/set_memory.h | 4 +-
arch/riscv/include/asm/swab.h | 87
++++++++++++++++
arch/riscv/include/asm/thread_info.h | 6 +-
arch/riscv/include/asm/uaccess.h | 2 +-
arch/riscv/include/asm/vdso.h | 4 +-
arch/riscv/include/asm/vdso/getrandom.h | 4 +-
arch/riscv/include/asm/vdso/gettimeofday.h | 4 +-
arch/riscv/include/asm/vdso/processor.h | 7 +-
arch/riscv/include/asm/vdso/vsyscall.h | 4 +-
arch/riscv/include/asm/vendor_extensions/mips.h | 37 +++++++
arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h | 22 ++++
arch/riscv/include/asm/vendorid_list.h | 1 +
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/include/uapi/asm/kvm.h | 2 +-
arch/riscv/include/uapi/asm/ptrace.h | 4 +-
arch/riscv/include/uapi/asm/sigcontext.h | 4 +-
arch/riscv/include/uapi/asm/vendor/mips.h | 3 +
arch/riscv/kernel/acpi.c | 3 +
arch/riscv/kernel/alternative.c | 5 +
arch/riscv/kernel/asm-offsets.c | 1 -
arch/riscv/kernel/cpufeature.c | 6 +-
arch/riscv/kernel/entry.S | 2 +-
arch/riscv/kernel/machine_kexec_file.c | 2 +-
arch/riscv/kernel/pi/Makefile | 2 +-
arch/riscv/kernel/pi/cmdline_early.c | 4 +-
arch/riscv/kernel/pi/fdt_early.c | 40 ++++++++
arch/riscv/kernel/pi/pi.h | 1 +
arch/riscv/kernel/probes/simulate-insn.c | 94
++++-------------
arch/riscv/kernel/sys_hwprobe.c | 18 ++--
arch/riscv/kernel/sys_riscv.c | 2 +-
arch/riscv/kernel/tests/Kconfig.debug | 12 +++
arch/riscv/kernel/tests/Makefile | 1 +
arch/riscv/kernel/tests/kprobes/Makefile | 1 +
arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S | 229
+++++++++++++++++++++++++++++++++++++++++
arch/riscv/kernel/tests/kprobes/test-kprobes.c | 56 ++++++++++
arch/riscv/kernel/tests/kprobes/test-kprobes.h | 24 +++++
arch/riscv/kernel/traps_misaligned.c | 144
+-------------------------
arch/riscv/kernel/vector.c | 2 +-
arch/riscv/kernel/vendor_extensions.c | 10 ++
arch/riscv/kernel/vendor_extensions/Makefile | 2 +
arch/riscv/kernel/vendor_extensions/mips.c | 22 ++++
arch/riscv/kernel/vendor_extensions/mips_hwprobe.c | 23 +++++
arch/riscv/kvm/vcpu_insn.c | 128
+----------------------
arch/riscv/mm/init.c | 12 ++-
drivers/acpi/Kconfig | 2 +-
include/asm-generic/rwonce.h | 2 +
lib/raid6/recov_rvv.c | 9 +-
lib/raid6/rvv.c | 362
+++++++++++++++++++++++++++++++++--------------------------------
lib/raid6/rvv.h | 17 ++++
lib/raid6/test/Makefile | 8 ++
tools/arch/riscv/include/asm/csr.h | 6 +-
tools/arch/riscv/include/asm/vdso/processor.h | 31 +++---
tools/testing/selftests/riscv/Makefile | 2 +-
tools/testing/selftests/riscv/misaligned/.gitignore | 1 +
tools/testing/selftests/riscv/misaligned/Makefile | 12 +++
tools/testing/selftests/riscv/misaligned/common.S | 33 ++++++
tools/testing/selftests/riscv/misaligned/fpu.S | 180
++++++++++++++++++++++++++++++++
tools/testing/selftests/riscv/misaligned/gp.S | 113
++++++++++++++++++++
tools/testing/selftests/riscv/misaligned/misaligned.c | 288
+++++++++++++++++++++++++++++++++++++++++++++++++++
98 files changed, 2019 insertions(+), 692 deletions(-)
create mode 100644 arch/riscv/errata/mips/Makefile
create mode 100644 arch/riscv/errata/mips/errata.c
create mode 100644 arch/riscv/include/asm/errata_list_vendors.h
create mode 100644 arch/riscv/include/asm/rwonce.h
create mode 100644 arch/riscv/include/asm/swab.h
create mode 100644 arch/riscv/include/asm/vendor_extensions/mips.h
create mode 100644 arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
create mode 100644 arch/riscv/include/uapi/asm/vendor/mips.h
create mode 100644 arch/riscv/kernel/tests/kprobes/Makefile
create mode 100644 arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S
create mode 100644 arch/riscv/kernel/tests/kprobes/test-kprobes.c
create mode 100644 arch/riscv/kernel/tests/kprobes/test-kprobes.h
create mode 100644 arch/riscv/kernel/vendor_extensions/mips.c
create mode 100644 arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
create mode 100644 tools/testing/selftests/riscv/misaligned/.gitignore
create mode 100644 tools/testing/selftests/riscv/misaligned/Makefile
create mode 100644 tools/testing/selftests/riscv/misaligned/common.S
create mode 100644 tools/testing/selftests/riscv/misaligned/fpu.S
create mode 100644 tools/testing/selftests/riscv/misaligned/gp.S
create mode 100644 tools/testing/selftests/riscv/misaligned/misaligned.c
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