[PATCH 2/5] riscv: misaligned: enable IRQs while handling misaligned accesses

[Alexandre Ghiti]

On 14/04/2025 14:34, Clément Léger wrote:
> We can safely reenable IRQs if they were enabled in the previous
> context. This allows to access user memory that could potentially
> trigger a page fault.
>
> Fixes: b686ecdeacf6 ("riscv: misaligned: Restrict user access to kernel memory")
> Signed-off-by: Clément Léger <cleger at rivosinc.com>
> ---
>   arch/riscv/kernel/traps.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index 55d9f3450398..3eecc2addc41 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -206,6 +206,11 @@ enum misaligned_access_type {
>   static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type type)
>   {
>   	irqentry_state_t state = irqentry_enter(regs);
> +	bool enable_irqs = !regs_irqs_disabled(regs);
> +
> +	/* Enable interrupts if they were enabled in the interrupted context. */
> +	if (enable_irqs)
> +		local_irq_enable();
>   
>   	if (type ==  MISALIGNED_LOAD) {
>   		if (handle_misaligned_load(regs))
> @@ -217,6 +222,9 @@ static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type
>   				      "Oops - store (or AMO) address misaligned");
>   	}
>   
> +	if (enable_irqs)
> +		local_irq_disable();
> +
>   	irqentry_exit(regs, state);
>   }
>   


Reviewed-by: Alexandre Ghiti <alexghiti at rivosinc.com>

Thanks,

Alex