[PATCH 5/7] phy: spacemit: add USB3 support for K1 PCIe/USB3 combo PHY

Ze Huang huangze at whut.edu.cn
Wed Apr 9 02:43:41 PDT 2025


On 4/7/25 9:28 PM, Krzysztof Kozlowski wrote:
> On 07/04/2025 14:38, Ze Huang wrote:
>> Add support for USB 3.0 mode on the K1 PCIe/USB3 combo PHY. Currently,
>> only USB mode is supported; PCIe support is not included in this change.
>>
>> Signed-off-by: Ze Huang <huangze at whut.edu.cn>
>> ---
>>   drivers/phy/spacemit/Kconfig          |   8 ++
>>   drivers/phy/spacemit/Makefile         |   1 +
>>   drivers/phy/spacemit/phy-k1-combphy.c | 229 ++++++++++++++++++++++++++++++++++
>>   3 files changed, 238 insertions(+)
>>
>> diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig
>> index f0c2a33f53cc810e71c6140ae957aa68a2b6ff0c..12749aba756329cf64fb9199055ba484fe05f3ab 100644
>> --- a/drivers/phy/spacemit/Kconfig
>> +++ b/drivers/phy/spacemit/Kconfig
>> @@ -10,3 +10,11 @@ config PHY_SPACEMIT_K1_USB2
>>   	help
>>   	  Enable this to support K1 USB 2.0 PHY driver. This driver takes care of
>>   	  enabling and clock setup and will be used by K1 udc/ehci/otg driver.
>> +
>> +config PHY_SPACEMIT_K1_COMBPHY
>> +	tristate "SpacemiT K1 PCIe/USB3 combo PHY support"
>> +	depends on OF
>> +	select GENERIC_PHY
>> +	default ARCH_SPACEMIT && USB_DWC3_SPACEMIT
>> +	help
>> +	  USB3/PCIe Combo PHY Support for SpacemiT K1 SoC
> Missing depends on ARCH_SPACEMIT || COMPILE_TEST

Will fix, thanks!

>
> ...
>
>
>> +	priv->phy = devm_phy_create(dev, NULL, &spacemit_combphy_ops);
>> +	if (IS_ERR(priv->phy))
>> +		return dev_err_probe(dev, PTR_ERR(priv->phy),
>> +				     "failed to create combphy\n");
>> +
>> +	dev_set_drvdata(dev, priv);
>> +	phy_set_drvdata(priv->phy, priv);
> Both make no sense. Look what this function does.

It does seem redundant at first glance, but pdev->dev is the parent of 
phy->dev.
pdev->dev->driver_data will be used in spacemit_combphy_xlate()
phy->dev->driver_data  will be used in phy_ops functions

I've checked some other drivers that did the same:
     - phy-zynqmp.c at lines 990 and 1026
     - phy-rockchip-samsung-hdptx.c at lines 1989 and 2000

>
> Best regards,
> Krzysztof
>
>



More information about the linux-riscv mailing list