[PATCH v3 0/2] Implement endianess swap macros for RISC-V

[Ben Dooks]

On 03/04/2025 21:34, Ignacio Encinas wrote:
> Motivated by [1]. A couple of things to note:
> 
> RISC-V needs a default implementation to fall back on. There is one
> available in include/uapi/linux/swab.h but that header can't be included
> from arch/riscv/include/asm/swab.h. Therefore, the first patch in this
> series moves the default implementation into asm-generic.
> 
> Tested with crc_kunit as pointed out here [2]. I can't provide
> performance numbers as I don't have RISC-V hardware yet.
> 
> [1] https://lore.kernel.org/all/20250302220426.GC2079@quark.localdomain/
> [2] https://lore.kernel.org/all/20250216225530.306980-1-ebiggers@kernel.org/
> 
> Signed-off-by: Ignacio Encinas <ignacio at iencinas.com>

I'll try and get these tested with my big-endian riscv qemu and verify
if they work there.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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