[RFC] riscv/entry: issue about a0/orig_a0 register and ENOSYS

[Eugene Syromiatnikov]

On Tue, Sep 17, 2024 at 01:59:23PM +0800, Celeste Liu wrote:
> On 2024-09-17 12:09, Celeste Liu wrote:
> [...]
> > Unfortunately, struct user_regs_struct is defined as below:
> > 
> >         struct user_regs_struct {
> >                 unsigned long pc;
> >         ...
> >                 unsigned long t6;
> >         };
> > 
> > It doesn't contain something like reserved[] as padding to leave the
> > space to add more registers from struct pt_regs!
> > The loongarch do the right thing as below:
> > 
> >         struct user_pt_regs {
> >                 /* Main processor registers. */
> >                 unsigned long regs[32];
> >         ...
> >                 unsigned long reserved[10];
> >         } __attribute__((aligned(8)));
> > 
> > RISC-V can't include orig_a0 in user_regs_struct without breaking UABI.
> > 
> > Need a discussion to decide to use which solution, or is there any
> > other better solution?

As another data point, AArch64 has NT_ARM_SYSTEM_CALL (introduced
in v3.19-rc1~59^2~16[3]) for the purposes of syscall number tampering.

> > [1]: https://github.com/strace/strace/issues/315
> > [2]: https://lore.kernel.org/linux-riscv/20240627071422.GA2626@altlinux.org/

[3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=766a85d7bc5d7f1ddd6de28bdb844eae45ec63b0