[PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx

[Andrew Lunn]

> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -210,6 +210,55 @@ i2c4: i2c at 4040000 {
>  			status = "disabled";
>  		};
>  
> +		gmac0: ethernet at 4070000 {
> +			compatible = "snps,dwmac-3.70a";
> +			reg = <0x04070000 0x10000>;
> +			clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>;
> +			clock-names = "stmmaceth", "ptp_ref";
> +			interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			phy-handle = <&phy0>;
> +			phy-mode = "rmii";
> +			rx-fifo-depth = <8192>;
> +			tx-fifo-depth = <8192>;
> +			snps,multicast-filter-bins = <0>;
> +			snps,perfect-filter-entries = <1>;
> +			snps,aal;
> +			snps,txpbl = <8>;
> +			snps,rxpbl = <8>;
> +			snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
> +			snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
> +			snps,axi-config = <&gmac0_stmmac_axi_setup>;
> +			status = "disabled";
> +
> +			mdio {
> +				compatible = "snps,dwmac-mdio";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				phy0: phy at 0 {
> +					compatible = "ethernet-phy-ieee802.3-c22";
> +					reg = <0>;
> +				};
> +			};

It is not clear to me what cv18xx.dtsi represents, and where the PHY
node should be, here, or in a .dts file. Is this a SOM, and the PHY is
on the SOM? 

	Andrew