[PATCH 04/13] RISC-V: KVM: Break down the __kvm_riscv_switch_to() into macros

Atish Patra atishp at atishpatra.org
Wed Oct 16 14:37:45 PDT 2024


On Fri, Jul 19, 2024 at 9:09 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> Break down the __kvm_riscv_switch_to() function into macros so that
> these macros can be later re-used by SBI NACL extension based low-level
> switch function.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  arch/riscv/kvm/vcpu_switch.S | 52 +++++++++++++++++++++++++++---------
>  1 file changed, 40 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu_switch.S b/arch/riscv/kvm/vcpu_switch.S
> index 3f8cbc21a644..9f13e5ce6a18 100644
> --- a/arch/riscv/kvm/vcpu_switch.S
> +++ b/arch/riscv/kvm/vcpu_switch.S
> @@ -11,11 +11,7 @@
>  #include <asm/asm-offsets.h>
>  #include <asm/csr.h>
>
> -       .text
> -       .altmacro
> -       .option norelax
> -
> -SYM_FUNC_START(__kvm_riscv_switch_to)
> +.macro SAVE_HOST_GPRS
>         /* Save Host GPRs (except A0 and T0-T6) */
>         REG_S   ra, (KVM_ARCH_HOST_RA)(a0)
>         REG_S   sp, (KVM_ARCH_HOST_SP)(a0)
> @@ -40,10 +36,12 @@ SYM_FUNC_START(__kvm_riscv_switch_to)
>         REG_S   s9, (KVM_ARCH_HOST_S9)(a0)
>         REG_S   s10, (KVM_ARCH_HOST_S10)(a0)
>         REG_S   s11, (KVM_ARCH_HOST_S11)(a0)
> +.endm
>
> +.macro SAVE_HOST_AND_RESTORE_GUEST_CSRS __resume_addr
>         /* Load Guest CSR values */
>         REG_L   t0, (KVM_ARCH_GUEST_SSTATUS)(a0)
> -       la      t1, .Lkvm_switch_return
> +       la      t1, \__resume_addr
>         REG_L   t2, (KVM_ARCH_GUEST_SEPC)(a0)
>
>         /* Save Host and Restore Guest SSTATUS */
> @@ -62,7 +60,9 @@ SYM_FUNC_START(__kvm_riscv_switch_to)
>         REG_S   t0, (KVM_ARCH_HOST_SSTATUS)(a0)
>         REG_S   t1, (KVM_ARCH_HOST_STVEC)(a0)
>         REG_S   t3, (KVM_ARCH_HOST_SSCRATCH)(a0)
> +.endm
>
> +.macro RESTORE_GUEST_GPRS
>         /* Restore Guest GPRs (except A0) */
>         REG_L   ra, (KVM_ARCH_GUEST_RA)(a0)
>         REG_L   sp, (KVM_ARCH_GUEST_SP)(a0)
> @@ -97,13 +97,9 @@ SYM_FUNC_START(__kvm_riscv_switch_to)
>
>         /* Restore Guest A0 */
>         REG_L   a0, (KVM_ARCH_GUEST_A0)(a0)
> +.endm
>
> -       /* Resume Guest */
> -       sret
> -
> -       /* Back to Host */
> -       .align 2
> -.Lkvm_switch_return:
> +.macro SAVE_GUEST_GPRS
>         /* Swap Guest A0 with SSCRATCH */
>         csrrw   a0, CSR_SSCRATCH, a0
>
> @@ -138,7 +134,9 @@ SYM_FUNC_START(__kvm_riscv_switch_to)
>         REG_S   t4, (KVM_ARCH_GUEST_T4)(a0)
>         REG_S   t5, (KVM_ARCH_GUEST_T5)(a0)
>         REG_S   t6, (KVM_ARCH_GUEST_T6)(a0)
> +.endm
>
> +.macro SAVE_GUEST_AND_RESTORE_HOST_CSRS
>         /* Load Host CSR values */
>         REG_L   t0, (KVM_ARCH_HOST_STVEC)(a0)
>         REG_L   t1, (KVM_ARCH_HOST_SSCRATCH)(a0)
> @@ -160,7 +158,9 @@ SYM_FUNC_START(__kvm_riscv_switch_to)
>         REG_S   t1, (KVM_ARCH_GUEST_A0)(a0)
>         REG_S   t2, (KVM_ARCH_GUEST_SSTATUS)(a0)
>         REG_S   t3, (KVM_ARCH_GUEST_SEPC)(a0)
> +.endm
>
> +.macro RESTORE_HOST_GPRS
>         /* Restore Host GPRs (except A0 and T0-T6) */
>         REG_L   ra, (KVM_ARCH_HOST_RA)(a0)
>         REG_L   sp, (KVM_ARCH_HOST_SP)(a0)
> @@ -185,6 +185,34 @@ SYM_FUNC_START(__kvm_riscv_switch_to)
>         REG_L   s9, (KVM_ARCH_HOST_S9)(a0)
>         REG_L   s10, (KVM_ARCH_HOST_S10)(a0)
>         REG_L   s11, (KVM_ARCH_HOST_S11)(a0)
> +.endm
> +
> +       .text
> +       .altmacro
> +       .option norelax
> +
> +       /*
> +        * Parameters:
> +        * A0 <= Pointer to struct kvm_vcpu_arch
> +        */
> +SYM_FUNC_START(__kvm_riscv_switch_to)
> +       SAVE_HOST_GPRS
> +
> +       SAVE_HOST_AND_RESTORE_GUEST_CSRS .Lkvm_switch_return
> +
> +       RESTORE_GUEST_GPRS
> +
> +       /* Resume Guest using SRET */
> +       sret
> +
> +       /* Back to Host */
> +       .align 2
> +.Lkvm_switch_return:
> +       SAVE_GUEST_GPRS
> +
> +       SAVE_GUEST_AND_RESTORE_HOST_CSRS
> +
> +       RESTORE_HOST_GPRS
>
>         /* Return to C code */
>         ret
> --
> 2.34.1
>

Reviewed-by: Atish Patra <atishp at rivosinc.com>

-- 
Regards,
Atish



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