[PATCH v2 0/3] riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI
Inochi Amaoto
inochiama at gmail.com
Wed Oct 9 15:44:06 PDT 2024
New version of T-HEAD C920 implement a fully featured ACLINT[1] device
(This core is used by Sophgo SG2044). This ACLINT device provides a
SSWI field to support fast S-mode IPI. This SSWI device is like the
MSWI device in CLINT/ACLINT, but for S-mode. The only thing is different
from the draft is that the T-HEAD version SSWI needs to write 0 on the
SSWI address to clear the IPI.
Add full support for T-HEAD C900 SSWI device.
[1] https://github.com/riscv/riscv-aclint
Change from v1:
1. patch 2: use computed reg offset to avoid uncessary reg additions
when setting/clearing irq.
2. patch 2: fix mulitple format issues and improve some comments.
3. patch 2: disable cpu irq when CPU is stopped.
Inochi Amaoto (3):
dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI
irqchip: add T-HEAD C900 ACLINT SSWI driver
riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers
.../thead,c900-aclint-sswi.yaml | 58 ++++++
arch/riscv/configs/defconfig | 1 +
drivers/irqchip/Kconfig | 10 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-thead-c900-aclint-sswi.c | 166 ++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
6 files changed, 237 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c
--
2.47.0
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