Page sizes supported by RISC-V

[Palmer Dabbelt]

On Sun, 29 Sep 2024 08:49:34 PDT (-0700), macro at orcam.me.uk wrote:
> On Sun, 29 Sep 2024, Jeff Law wrote:
>
>> I strongly suspect the lack of specification here is mean to give degrees of
>> freedom to the implementors, but sometimes those writing the specs don't
>> really understand the implication of leaving things like this unspecified and
>> how much pain it really causes in the end.
>
>  But 64KiB pages have already been mentioned, so sanctioning this possible
> size in binutils (or LD specifically) would be a reasonable thing to do at
> this time IMHO.
>
>  FWIW out of the plethora sizes (from 1KiB up to 256TiB) possible to have
> in hardware (and available on a page-by-page basis) the MIPS/Linux port
> has settled on a fixed for a given kernel configuration page size choice
> among 4KiB, 16KiB, 64KiB, and this has been reflected in binutils, so
> perhaps copying the MIPS bits might be the path of least resistance.

This comes up every once in a while and we end generally end up deciding 
we're just stuck with a 4KiB base on RISC-V.  We've got 64KiB fused 
pages in the ISA now, so getting userspace 64KiB aligned whenever 
possible would be a nice to have, but that doesn't get rid of the 4KiB 
base page size.

When someone wants larger base page sizes then they're going to be stuck 
with all the pain that every other port had to go through to make that 
all fit together.  It's a bummer we didn't sort that out ahead of time, 
but we've got a lot of baggage to unwind ;)

>   Maciej
>
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