[PATCH] riscv/futex: Optimize atomic cmpxchg

[Andrea Parri]

On Wed, Nov 13, 2024 at 10:33:21AM -0800, Davidlohr Bueso wrote:
> Remove redundant release/acquire barriers, optimizing the lr/sc sequence
> to provide conditional RCsc synchronization, per the RVWMO.
> 
> Signed-off-by: Davidlohr Bueso <dave at stgolabs.net>
> ---
>  arch/riscv/include/asm/futex.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h
> index fc8130f995c1..72be100afa23 100644
> --- a/arch/riscv/include/asm/futex.h
> +++ b/arch/riscv/include/asm/futex.h
> @@ -85,7 +85,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
>  
>  	__enable_user_access();
>  	__asm__ __volatile__ (
> -	"1:	lr.w.aqrl %[v],%[u]			\n"
> +	"1:	lr.w %[v],%[u]			        \n"
>  	"	bne %[v],%z[ov],3f			\n"
>  	"2:	sc.w.aqrl %[t],%z[nv],%[u]		\n"
>  	"	bnez %[t],1b				\n"

atomic_cmpxchg() uses yet another scheme, but this does also look good
to me: FWIW,

Reviewed-by: Andrea Parri <parri.andrea at gmail.com>

  Andrea