[PATCH 2/3] irqchip: Add the Sophgo SG2042 MSI interrupt controller

[Thomas Gleixner]

On Wed, Nov 13 2024 at 14:43, Chen Wang wrote:
> On 2024/11/13 14:14, Thomas Gleixner wrote:
>>> +
>>> +	middle_domain = irq_domain_create_hierarchy(plic_domain, 0, priv->num_irqs,
>>> +						    fwnode,
>>> +						    &pch_msi_middle_domain_ops,
>>> +						    priv);
>> So now you have created a domain. How is that supposed to be used by the
>> PCI layer?
>
> Here I create the domain and attached it to the fwnode. In PCI driver, 
> it can set this msi controller as its ""interrupt-parent" and find the 
> domain attached as below:
>
> static int pcie_probe(struct platform_device *pdev)
> {
>      struct device *dev = &pdev->dev;
>      parent_node = of_irq_find_parent(dev->of_node);
>      parent_domain = irq_find_host(parent_node);
>      ...
> }

I assume you then want to create a global PCI/MSI domain via
pci_msi_create_irq_domain(), right?

That's not the preferred way to do that. Any new implementation should
use the MSI parent model, where each PCI device creates it's own per
device MSI domain with the MSI interrupt controller as parent
domain.

There is a library with helper functions, irq-msi-lib.[ch]. See
gicv2m_allocate_domains() or pch_msi_init_domains() for reference.

Thanks

        tglx