[GIT PULL] RISC-V Fixes for 6.10-rc2

[Palmer Dabbelt]

The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0:

  Linux 6.10-rc1 (2024-05-26 15:20:12 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.10-rc2

for you to fetch changes up to 1d84afaf02524d2558e8ca3ca169be2ef720380b:

  riscv: Fix fully ordered LR/SC xchg[8|16]() implementations (2024-05-30 09:43:14 -0700)

----------------------------------------------------------------
RISC-V Fixes for 6.10-rc2

* A fix to avoid pt_regs aliasing with idle thread stacks on secondary
  harts.
* HAVE_ARCH_HUGE_VMAP is enabled on XIP kernels, which fixes boot issues
  on XIP systems with huge pages.
* An update to the uABI documentation clarifying that only scalar
  misaligned accesses were grandfathered in as supported, as the vector
  extension did not exist at the time the uABI was frozen.
* A fix for the recently-added byte/half atomics to avoid losing the
  fully ordered decorations.

----------------------------------------------------------------
Alexandre Ghiti (1):
      riscv: Fix fully ordered LR/SC xchg[8|16]() implementations

Nam Cao (1):
      riscv: enable HAVE_ARCH_HUGE_VMAP for XIP kernel

Palmer Dabbelt (1):
      Documentation: RISC-V: uabi: Only scalar misaligned loads are supported

Sergey Matyukevich (1):
      riscv: prevent pt_regs corruption for secondary idle threads

 Documentation/arch/riscv/uabi.rst    |  4 +++-
 arch/riscv/Kconfig                   |  2 +-
 arch/riscv/include/asm/cmpxchg.h     | 22 ++++++++++++----------
 arch/riscv/kernel/cpu_ops_sbi.c      |  2 +-
 arch/riscv/kernel/cpu_ops_spinwait.c |  3 +--
 5 files changed, 18 insertions(+), 15 deletions(-)