[PATCH 2/4] riscv: entry: Balance vector context nesting

[Samuel Holland]

Vector context management is the last thing done before jumping to C
code, so it should be the first thing done after returning from C code.
This also improves efficiency: riscv_v_context_nesting_end() clobbers
the saved value of the status CSR, so currently ret_from_exception()
must reload it. This is not necessary if riscv_v_context_nesting_end()
is called first.

Signed-off-by: Samuel Holland <samuel.holland at sifive.com>
---

 arch/riscv/kernel/entry.S | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 4c5b22cb7381..d13d1aad7649 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -120,6 +120,11 @@ ASM_NOKPROBE(handle_exception)
  *  - ret_from_fork
  */
 SYM_CODE_START_NOALIGN(ret_from_exception)
+#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
+	move a0, sp
+	call riscv_v_context_nesting_end
+#endif
+
 	REG_L s0, PT_STATUS(sp)
 #ifdef CONFIG_RISCV_M_MODE
 	/* the MPP value is too large to be used as an immediate arg for addi */
@@ -143,10 +148,6 @@ SYM_CODE_START_NOALIGN(ret_from_exception)
 	 */
 	csrw CSR_SCRATCH, tp
 1:
-#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
-	move a0, sp
-	call riscv_v_context_nesting_end
-#endif
 	REG_L a0, PT_STATUS(sp)
 	/*
 	 * The current load reservation is effectively part of the processor's
-- 
2.44.1