[PATCH v3 2/2] RISC-V: separate Zbb optimisations requiring and not requiring toolchain support

Conor Dooley conor.dooley at microchip.com
Tue May 28 23:30:15 PDT 2024


On Wed, May 29, 2024 at 01:01:24AM +0000, Wang, Xiao W wrote:
> > From: Conor Dooley <conor at kernel.org>
> > Sent: Tuesday, May 28, 2024 7:11 PM
> > -	ALTERNATIVE("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB,
> > CONFIG_RISCV_ISA_ZBB)
> > +	__ALTERNATIVE_CFG("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB,
> > +		IS_ENABLED(CONFIG_RISCV_ISA_ZBB_ALT) &&
> > IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB))
> 
> s/CONFIG_RISCV_ISA_ZBB_ALT/ CONFIG_RISCV_ISA_ZBB
> Same issue for below changes in strn*.S

I could have sworn I grepped for it and there was nothing, obviously
not... Thanks, I'll fix it up in a new version.

Thanks,
Conor
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