[PATCH v2] riscv: lib: relax assembly constraints in hweight

[Wang, Xiao W]

> -----Original Message-----
> From: Qingfang Deng <dqfext at gmail.com>
> Sent: Monday, May 27, 2024 5:24 PM
> To: Paul Walmsley <paul.walmsley at sifive.com>; Palmer Dabbelt
> <palmer at dabbelt.com>; Albert Ou <aou at eecs.berkeley.edu>; linux-
> riscv at lists.infradead.org; linux-kernel at vger.kernel.org
> Cc: Wang, Xiao W <xiao.w.wang at intel.com>; Qingfang Deng
> <qingfang.deng at siflower.com.cn>
> Subject: [PATCH v2] riscv: lib: relax assembly constraints in hweight
> 
> From: Qingfang Deng <qingfang.deng at siflower.com.cn>
> 
> rd and rs don't have to be the same. In some cases where rs needs to be
> saved for later usage, this will save us some mv instructions.
> 
> Signed-off-by: Qingfang Deng <qingfang.deng at siflower.com.cn>
> ---
> v2: updated title as suggested by Xiao.
> 
>  arch/riscv/include/asm/arch_hweight.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/arch_hweight.h
> b/arch/riscv/include/asm/arch_hweight.h
> index 85b2c443823e..613769b9cdc9 100644
> --- a/arch/riscv/include/asm/arch_hweight.h
> +++ b/arch/riscv/include/asm/arch_hweight.h
> @@ -26,9 +26,9 @@ static __always_inline unsigned int
> __arch_hweight32(unsigned int w)
> 
>  	asm (".option push\n"
>  	     ".option arch,+zbb\n"
> -	     CPOPW "%0, %0\n"
> +	     CPOPW "%0, %1\n"
>  	     ".option pop\n"
> -	     : "+r" (w) : :);
> +	     : "=r" (w) : "r" (w) :);
> 
>  	return w;
> 
> @@ -57,9 +57,9 @@ static __always_inline unsigned long
> __arch_hweight64(__u64 w)
> 
>  	asm (".option push\n"
>  	     ".option arch,+zbb\n"
> -	     "cpop %0, %0\n"
> +	     "cpop %0, %1\n"
>  	     ".option pop\n"
> -	     : "+r" (w) : :);
> +	     : "=r" (w) : "r" (w) :);
> 
>  	return w;
> 
> --
> 2.34.1

Reviewed-by: Xiao Wang <xiao.w.wang at intel.com>