[PATCH] riscv: hweight: relax assembly constraints

[Wang, Xiao W]

> -----Original Message-----
> From: Qingfang Deng <dqfext at gmail.com>
> Sent: Friday, May 24, 2024 2:05 PM
> To: Wang, Xiao W <xiao.w.wang at intel.com>
> Cc: Paul Walmsley <paul.walmsley at sifive.com>; Palmer Dabbelt
> <palmer at dabbelt.com>; Albert Ou <aou at eecs.berkeley.edu>; linux-
> riscv at lists.infradead.org; linux-kernel at vger.kernel.org; Qingfang Deng
> <qingfang.deng at siflower.com.cn>
> Subject: Re: [PATCH] riscv: hweight: relax assembly constraints
> 
> Hi,
> 
> On Fri, May 24, 2024 at 9:02 AM Wang, Xiao W <xiao.w.wang at intel.com>
> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Qingfang Deng <dqfext at gmail.com>
> > > Sent: Thursday, May 23, 2024 5:43 PM
> > > To: Paul Walmsley <paul.walmsley at sifive.com>; Palmer Dabbelt
> > > <palmer at dabbelt.com>; Albert Ou <aou at eecs.berkeley.edu>; linux-
> > > riscv at lists.infradead.org; linux-kernel at vger.kernel.org
> > > Cc: Wang, Xiao W <xiao.w.wang at intel.com>; Qingfang Deng
> > > <qingfang.deng at siflower.com.cn>
> > > Subject: [PATCH] riscv: hweight: relax assembly constraints
> > >
> > > From: Qingfang Deng <qingfang.deng at siflower.com.cn>
> > >
> > > rd and rs don't have to be the same.
> > >
> > > Signed-off-by: Qingfang Deng <qingfang.deng at siflower.com.cn>
> > > ---
> > >  arch/riscv/include/asm/arch_hweight.h | 8 ++++----
> > >  1 file changed, 4 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/arch_hweight.h
> > > b/arch/riscv/include/asm/arch_hweight.h
> > > index 85b2c443823e..613769b9cdc9 100644
> > > --- a/arch/riscv/include/asm/arch_hweight.h
> > > +++ b/arch/riscv/include/asm/arch_hweight.h
> > > @@ -26,9 +26,9 @@ static __always_inline unsigned int
> > > __arch_hweight32(unsigned int w)
> > >
> > >       asm (".option push\n"
> > >            ".option arch,+zbb\n"
> > > -          CPOPW "%0, %0\n"
> > > +          CPOPW "%0, %1\n"
> > >            ".option pop\n"
> > > -          : "+r" (w) : :);
> > > +          : "=r" (w) : "r" (w) :);
> >
> > The above code piece takes variable "w" as both input and output, so
> intuitively, the previous
> > patch made rs and rd the same.
> > Though rs and rd can be different, do you see performance difference with
> this change?
> > Or any analysis from assembly dump?
> 
> By making rs and rd different, we can save some `mv` instructions.

OK, I guess in some cases, the original data needs be saved for later usage.
Then, we can relax the assembly constraint here and gives flexibility to compiler
For optimization.

It's better to start the patch tile with " riscv: lib:", maybe you can make the title as:
riscv: lib: relax assembly constraints in hweight

BRs,
Xiao

> 
> >
> > BRs,
> > Xiao
> >
> > >
> > >       return w;
> > >
> > > @@ -57,9 +57,9 @@ static __always_inline unsigned long
> > > __arch_hweight64(__u64 w)
> > >
> > >       asm (".option push\n"
> > >            ".option arch,+zbb\n"
> > > -          "cpop %0, %0\n"
> > > +          "cpop %0, %1\n"
> > >            ".option pop\n"
> > > -          : "+r" (w) : :);
> > > +          : "=r" (w) : "r" (w) :);
> > >
> > >       return w;
> > >
> > > --
> > > 2.34.1
> >