[PATCH v1] RISC-V: separate Zbb optimisations requiring and not requiring toolchain support

[Conor Dooley]

On Wed, May 15, 2024 at 09:58:50PM -0700, Charlie Jenkins wrote:
> On Wed, May 15, 2024 at 04:27:40PM +0100, Conor Dooley wrote:

> > diff --git a/arch/riscv/lib/strlen.S b/arch/riscv/lib/strlen.S
> > index 8ae3064e45ff..3ab1310a7b83 100644
> > --- a/arch/riscv/lib/strlen.S
> > +++ b/arch/riscv/lib/strlen.S
> > @@ -8,7 +8,7 @@
> >  /* int strlen(const char *s) */
> >  SYM_FUNC_START(strlen)
> >  
> > -	ALTERNATIVE("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
> > +	ALTERNATIVE("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB_ALT)

> I am missing why these str functions are changed to use
> CONFIG_RISCV_ISA_ZBB_ALT when the __arch_hweight* functions were left as
> using CONFIG_RISCV_ISA_ZBB in their alternatives.

I don't think I missed anything in the __arch_hweight*() functions,
their final argument is 1 and they are not conditional on a config
option as the whole block of code they're in is wrapped in ifdeffery:

# ifdef CONFIG_RISCV_ISA_ZBB_ALT
	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
				      RISCV_ISA_EXT_ZBB, 1)
			  : : : : legacy);

Cheers,
Conor.
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