[PATCH v2] RISC-V: fix Andes errata build issues

Conor Dooley conor at kernel.org
Wed May 15 09:56:30 PDT 2024


On Wed, May 15, 2024 at 09:49:24AM -0700, Charlie Jenkins wrote:
> On Wed, May 15, 2024 at 05:09:34PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley at microchip.com>
> > 
> > Commit e47c37c24024 ("riscv: Introduce vendor variants of extension
> > helpers") added includes for the new vendor_extensions.h header in
> > the T-Head and SiFive errata handling code but didn't do so for Andes,
> > resulting in allmodconfig build issues when commit 589e2fc85850
> > ("riscv: Convert xandespmu to use the vendor extension framework")
> > added a user of a macro defined there.
> > 
> > Fixes: 589e2fc85850 ("riscv: Convert xandespmu to use the vendor extension framework")
> > Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

> 
> I was going to fix this in my next version but was waiting for the
> reviews on the thead stuff. I wasn't anticipating these patches to be
> able to jump the queue :)

Yah, the reason for that is I asked him to take the non-vector parts of
the series as 6.10 material so that we'd have less stuff movin' around
in cpufeatures.c so that Clement's Zc* + validation changes wouldn't run
into a bunch of conflicts etc. Same reason that I pushed for getting
Andy's vector subset stuff merged today, but that mighta been before you
hopped in.

Cheers,
Conor.
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