[PATCH 2/7] perf vendor events riscv: Remove leading zeroes
Samuel Holland
samuel.holland at sifive.com
Wed May 8 19:14:55 PDT 2024
The EventCode field (as stored in the mhpmeventN CSRs) is actually 56
bits wide, but there is no need to keep leading zeroes in the JSON
files. Remove them to simplify review of the following change, which
regenerates the files in a way that does not include leading zeroes.
This change was performed automatically with `sed -i "s/0x0*/0x/"`.
Signed-off-by: Samuel Holland <samuel.holland at sifive.com>
---
.../arch/riscv/sifive/bullet/instruction.json | 32 +++++++++----------
.../arch/riscv/sifive/bullet/memory.json | 12 +++----
.../arch/riscv/sifive/bullet/microarch.json | 22 ++++++-------
3 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
index 5eab718c9256..d5c370f70819 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
@@ -1,82 +1,82 @@
[
{
"EventName": "EXCEPTION_TAKEN",
- "EventCode": "0x0000100",
+ "EventCode": "0x100",
"BriefDescription": "Exception taken"
},
{
"EventName": "INTEGER_LOAD_RETIRED",
- "EventCode": "0x0000200",
+ "EventCode": "0x200",
"BriefDescription": "Integer load instruction retired"
},
{
"EventName": "INTEGER_STORE_RETIRED",
- "EventCode": "0x0000400",
+ "EventCode": "0x400",
"BriefDescription": "Integer store instruction retired"
},
{
"EventName": "ATOMIC_MEMORY_RETIRED",
- "EventCode": "0x0000800",
+ "EventCode": "0x800",
"BriefDescription": "Atomic memory operation retired"
},
{
"EventName": "SYSTEM_INSTRUCTION_RETIRED",
- "EventCode": "0x0001000",
+ "EventCode": "0x1000",
"BriefDescription": "System instruction retired"
},
{
"EventName": "INTEGER_ARITHMETIC_RETIRED",
- "EventCode": "0x0002000",
+ "EventCode": "0x2000",
"BriefDescription": "Integer arithmetic instruction retired"
},
{
"EventName": "CONDITIONAL_BRANCH_RETIRED",
- "EventCode": "0x0004000",
+ "EventCode": "0x4000",
"BriefDescription": "Conditional branch retired"
},
{
"EventName": "JAL_INSTRUCTION_RETIRED",
- "EventCode": "0x0008000",
+ "EventCode": "0x8000",
"BriefDescription": "JAL instruction retired"
},
{
"EventName": "JALR_INSTRUCTION_RETIRED",
- "EventCode": "0x0010000",
+ "EventCode": "0x10000",
"BriefDescription": "JALR instruction retired"
},
{
"EventName": "INTEGER_MULTIPLICATION_RETIRED",
- "EventCode": "0x0020000",
+ "EventCode": "0x20000",
"BriefDescription": "Integer multiplication instruction retired"
},
{
"EventName": "INTEGER_DIVISION_RETIRED",
- "EventCode": "0x0040000",
+ "EventCode": "0x40000",
"BriefDescription": "Integer division instruction retired"
},
{
"EventName": "FP_LOAD_RETIRED",
- "EventCode": "0x0080000",
+ "EventCode": "0x80000",
"BriefDescription": "Floating-point load instruction retired"
},
{
"EventName": "FP_STORE_RETIRED",
- "EventCode": "0x0100000",
+ "EventCode": "0x100000",
"BriefDescription": "Floating-point store instruction retired"
},
{
"EventName": "FP_ADDITION_RETIRED",
- "EventCode": "0x0200000",
+ "EventCode": "0x200000",
"BriefDescription": "Floating-point addition retired"
},
{
"EventName": "FP_MULTIPLICATION_RETIRED",
- "EventCode": "0x0400000",
+ "EventCode": "0x400000",
"BriefDescription": "Floating-point multiplication retired"
},
{
"EventName": "FP_FUSEDMADD_RETIRED",
- "EventCode": "0x0800000",
+ "EventCode": "0x800000",
"BriefDescription": "Floating-point fused multiply-add retired"
},
{
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
index be1a46312ac3..ba3168f8a4cd 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
@@ -1,32 +1,32 @@
[
{
"EventName": "ICACHE_RETIRED",
- "EventCode": "0x0000102",
+ "EventCode": "0x102",
"BriefDescription": "Instruction cache miss"
},
{
"EventName": "DCACHE_MISS_MMIO_ACCESSES",
- "EventCode": "0x0000202",
+ "EventCode": "0x202",
"BriefDescription": "Data cache miss or memory-mapped I/O access"
},
{
"EventName": "DCACHE_WRITEBACK",
- "EventCode": "0x0000402",
+ "EventCode": "0x402",
"BriefDescription": "Data cache write-back"
},
{
"EventName": "INST_TLB_MISS",
- "EventCode": "0x0000802",
+ "EventCode": "0x802",
"BriefDescription": "Instruction TLB miss"
},
{
"EventName": "DATA_TLB_MISS",
- "EventCode": "0x0001002",
+ "EventCode": "0x1002",
"BriefDescription": "Data TLB miss"
},
{
"EventName": "UTLB_MISS",
- "EventCode": "0x0002002",
+ "EventCode": "0x2002",
"BriefDescription": "UTLB miss"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
index 50ffa55418cb..8036e72fb0d4 100644
--- a/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
+++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
@@ -1,57 +1,57 @@
[
{
"EventName": "ADDRESSGEN_INTERLOCK",
- "EventCode": "0x0000101",
+ "EventCode": "0x101",
"BriefDescription": "Address-generation interlock"
},
{
"EventName": "LONGLAT_INTERLOCK",
- "EventCode": "0x0000201",
+ "EventCode": "0x201",
"BriefDescription": "Long-latency interlock"
},
{
"EventName": "CSR_READ_INTERLOCK",
- "EventCode": "0x0000401",
+ "EventCode": "0x401",
"BriefDescription": "CSR read interlock"
},
{
"EventName": "ICACHE_ITIM_BUSY",
- "EventCode": "0x0000801",
+ "EventCode": "0x801",
"BriefDescription": "Instruction cache/ITIM busy"
},
{
"EventName": "DCACHE_DTIM_BUSY",
- "EventCode": "0x0001001",
+ "EventCode": "0x1001",
"BriefDescription": "Data cache/DTIM busy"
},
{
"EventName": "BRANCH_DIRECTION_MISPREDICTION",
- "EventCode": "0x0002001",
+ "EventCode": "0x2001",
"BriefDescription": "Branch direction misprediction"
},
{
"EventName": "BRANCH_TARGET_MISPREDICTION",
- "EventCode": "0x0004001",
+ "EventCode": "0x4001",
"BriefDescription": "Branch/jump target misprediction"
},
{
"EventName": "PIPE_FLUSH_CSR_WRITE",
- "EventCode": "0x0008001",
+ "EventCode": "0x8001",
"BriefDescription": "Pipeline flush from CSR write"
},
{
"EventName": "PIPE_FLUSH_OTHER_EVENT",
- "EventCode": "0x0010001",
+ "EventCode": "0x10001",
"BriefDescription": "Pipeline flush from other event"
},
{
"EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
- "EventCode": "0x0020001",
+ "EventCode": "0x20001",
"BriefDescription": "Integer multiplication interlock"
},
{
"EventName": "FP_INTERLOCK",
- "EventCode": "0x0040001",
+ "EventCode": "0x40001",
"BriefDescription": "Floating-point interlock"
}
]
\ No newline at end of file
--
2.44.0
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