[PATCH 1/3] spi: spi-microchip-core: Add support for GPIO based CS

[Conor Dooley]

On Thu, May 02, 2024 at 03:34:08PM +0100, Prajna Rajendra Kumar wrote:
> The SPI controller within the PolarFire SoC is capable of handling
> multiple CS, but only one CS line is wired in the MSS. Therefore,
> use GPIO descriptors to configure additional CS lines.
> 
> Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar at microchip.com>

Acked-by: Conor Dooley <conor.dooley at microchip.com>
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