[PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

[Joshua Yeong]

Hi Conor,

> -----Original Message-----
> From: Conor Dooley <conor.dooley at microchip.com>
> Sent: Wednesday, March 20, 2024 4:09 PM
> To: Conor Dooley <conor at kernel.org>
> Cc: Joshua Yeong <joshua.yeong at starfivetech.com>;
> paul.walmsley at sifive.com; palmer at dabbelt.com; aou at eecs.berkeley.edu;
> geert+renesas at glider.be; prabhakar.mahadev-lad.rj at bp.renesas.com;
> alexghiti at rivosinc.com; evan at rivosinc.com; ajones at ventanamicro.com;
> heiko at sntech.de; guoren at kernel.org; uwu at icenowy.me;
> jszhang at kernel.org; robh+dt at kernel.org; krzysztof.kozlowski+dt at linaro.org;
> conor+dt at kernel.org; Leyfoon Tan <leyfoon.tan at starfivetech.com>; JeeHeng
> Sia <jeeheng.sia at starfivetech.com>; linux-riscv at lists.infradead.org; linux-
> kernel at vger.kernel.org; devicetree at vger.kernel.org
> Subject: Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller
> 
> On Sun, Mar 17, 2024 at 03:01:05PM +0000, Conor Dooley wrote:
> > On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> > > StarFive's StarLink-500 Cache Controller flush/invalidates cache
> > > using non- conventional CMO method. This driver provides the cache
> > > handling on StarFive RISC-V SoC.
> >
> > Unlike the other "non-conventional" CMO methods, the jh8100 does not
> > pre-date the Zicbom extension. Why has that not been implemented?
> 
> Stefan pointed out on IRC yesterday that one of the main selling points is the
> ease of operating on large ranges.
> 
> > How many peripherals on the jh8100 rely on non-coherent DMA?

JH8100 integrates in-house matured/stable CPU but it is a bit dated today.
However, our newer generation of CPU should already support this extension.

Most of the peripherals are coherent except mainly multimedia peripheral.

Regards,
Joshua

> >
> > Cheers,
> > Conor.
>