[v2, 6/7] riscv: hwprobe: add zve Vector subextensions into hwprobe interface

[Clément Léger]

On 14/03/2024 15:25, Andy Chiu wrote:
> The following Vector subextensions for "embedded" platforms are added
> into RISCV_HWPROBE_KEY_IMA_EXT_0:
>  - ZVE32X
>  - ZVE32F
>  - ZVE64X
>  - ZVE64F
>  - ZVE64D
> 
> Extensions end with X mean the platform don't have a Vector FPU.

Maybe rephrase it like that:

"Extensions ending with an X indicates that the platform doesn't have a
vector FPU"

> Extensions end with F/D mean whether single (F) or double (D) precision

"Extensions ending with F/D mean that whether single (F) or double (D)
precision vector operation is supported"

> Vector operation is supported.
> 
> The number 32 or 64 follows from ZVE tells the maximum element length.
> 
> Signed-off-by: Andy Chiu <andy.chiu at sifive.com>
> ---
> Changelog v2:
>  - zve* extensions in hwprobe depends on whether kernel supports v, so
>    include them after has_vector(). Fix a typo. (Clément)
> ---
>  Documentation/arch/riscv/hwprobe.rst  | 15 +++++++++++++++
>  arch/riscv/include/uapi/asm/hwprobe.h |  5 +++++
>  arch/riscv/kernel/sys_hwprobe.c       |  5 +++++
>  3 files changed, 25 insertions(+)
> 
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index b2bcc9eed9aa..d0b02e012e5d 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -188,6 +188,21 @@ The following keys are defined:
>         manual starting from commit 95cf1f9 ("Add changes requested by Ved
>         during signoff")
>  
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
>  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
>    information about the selected set of processors.
>  
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 9f2a8e3ff204..b9a0876e969f 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -59,6 +59,11 @@ struct riscv_hwprobe {
>  #define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
>  #define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
>  #define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
> +#define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 36)
> +#define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 37)
> +#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 38)
> +#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 39)
> +#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 40)
>  #define RISCV_HWPROBE_KEY_CPUPERF_0	5
>  #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
>  #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index a7c56b41efd2..db7495001f27 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -113,6 +113,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>  		EXT_KEY(ZICOND);
>  
>  		if (has_vector()) {
> +			EXT_KEY(ZVE32X);
> +			EXT_KEY(ZVE32F);
> +			EXT_KEY(ZVE64X);
> +			EXT_KEY(ZVE64F);
> +			EXT_KEY(ZVE64D);
>  			EXT_KEY(ZVBB);
>  			EXT_KEY(ZVBC);
>  			EXT_KEY(ZVKB);

With commit typo fixed,

Reviewed-by: Clément Léger <cleger at rivosinc.com>

Thanks,

Clément