[v1, 5/6] riscv: hwprobe: add zve Vector subextesnions into hwprobe interface

[Andy Chiu]

On Tue, Mar 12, 2024 at 8:42 PM Clément Léger <cleger at rivosinc.com> wrote:
>
>
>
> On 12/03/2024 13:36, Andy Chiu wrote:
> > The following Vector subextensions for "embedded" platforms are added
> > into RISCV_HWPROBE_KEY_IMA_EXT_0:
> >  - ZVE32X
> >  - ZVE32F
> >  - ZVE64X
> >  - ZVE64F
> >  - ZVE64D
> >
> > Extensions end with X mean the platform don't have a Vector FPU.
> > Extensions end with F/D mean whether single (F) or double (D) precision
> > Vector operation is supported.
> >
> > The number 32 or 64 follows from ZVE tells the maximum element length.
> >
> > Signed-off-by: Andy Chiu <andy.chiu at sifive.com>
> > ---
> >  Documentation/arch/riscv/hwprobe.rst  | 15 +++++++++++++++
> >  arch/riscv/include/uapi/asm/hwprobe.h |  5 +++++
> >  arch/riscv/kernel/sys_hwprobe.c       |  5 +++++
> >  3 files changed, 25 insertions(+)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index b2bcc9eed9aa..d0b02e012e5d 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -188,6 +188,21 @@ The following keys are defined:
> >         manual starting from commit 95cf1f9 ("Add changes requested by Ved
> >         during signoff")
> >
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> >  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
> >    information about the selected set of processors.
> >
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 9f2a8e3ff204..b9a0876e969f 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -59,6 +59,11 @@ struct riscv_hwprobe {
> >  #define              RISCV_HWPROBE_EXT_ZTSO          (1ULL << 33)
> >  #define              RISCV_HWPROBE_EXT_ZACAS         (1ULL << 34)
> >  #define              RISCV_HWPROBE_EXT_ZICOND        (1ULL << 35)
> > +#define              RISCV_HWPROBE_EXT_ZVE32X        (1ULL << 36)
> > +#define              RISCV_HWPROBE_EXT_ZVE32F        (1ULL << 37)
> > +#define              RISCV_HWPROBE_EXT_ZVE64X        (1ULL << 38)
> > +#define              RISCV_HWPROBE_EXT_ZVE64F        (1ULL << 39)
> > +#define              RISCV_HWPROBE_EXT_ZVE64D        (1ULL << 40)
> >  #define RISCV_HWPROBE_KEY_CPUPERF_0  5
> >  #define              RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
> >  #define              RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index a7c56b41efd2..2500d175ed66 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -111,6 +111,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> >               EXT_KEY(ZTSO);
> >               EXT_KEY(ZACAS);
> >               EXT_KEY(ZICOND);
> > +             EXT_KEY(ZVE32X);
> > +             EXT_KEY(ZVE32F);
> > +             EXT_KEY(ZVE64X);
> > +             EXT_KEY(ZVE64F);
> > +             EXT_KEY(ZVE64D);
>
> Hi Andy,
>
> I'm not sure but since these extensions are conditioned by the fact
> vector should be supported by the kernel, they probably needs to be put
> under the if below:
>
> >
> >               if (has_vector()) {
>
>                         <--- Here --->
> >                       EXT_KEY(ZVBB);

Yes, it makes sense. I will add them under this condition. Combined
with the last patch on this series, it would be something like this in
the end.

if (has_vector(ZVE32X)) {
        <-- Here -->
        EXT_KEY(ZVBB);
}

>
> Thanks !
>
> Clément

Thanks,
Andy