[v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
Clément Léger
cleger at rivosinc.com
Tue Mar 12 05:51:02 PDT 2024
On 12/03/2024 13:36, Andy Chiu wrote:
> Multiple Vector subextensions are added. Also, the patch takes care of
> the dependencies of Vector subextensions by macro expansions. So, if
> some "embedded" platform only reports "zve64f" on the ISA string, the
> parser is able to expand it to zve32x zve32f zve64x and zve64f.
>
> Signed-off-by: Andy Chiu <andy.chiu at sifive.com>
> ---
> arch/riscv/include/asm/hwcap.h | 5 +++++
> arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
> 2 files changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5340f818746b..24efea44f1ab 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,11 @@
> #define RISCV_ISA_EXT_ZFA 71
> #define RISCV_ISA_EXT_ZTSO 72
> #define RISCV_ISA_EXT_ZACAS 73
> +#define RISCV_ISA_EXT_ZVE32X 74
> +#define RISCV_ISA_EXT_ZVE32F 75
> +#define RISCV_ISA_EXT_ZVE64X 76
> +#define RISCV_ISA_EXT_ZVE64F 77
> +#define RISCV_ISA_EXT_ZVE64D 78
>
> #define RISCV_ISA_EXT_MAX 128
> #define RISCV_ISA_EXT_INVALID U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8986ceb58188..3aa0df3f3b41 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
> RISCV_ISA_EXT_ZVKB
> };
>
> +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST \
> + RISCV_ISA_EXT_ZVE32F, \
> + RISCV_ISA_EXT_ZVE32X,
> +
> +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \
> + RISCV_ISA_EXT_ZVE64F, \
> + RISCV_ISA_EXT_ZVE64X, \
> + RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +
> +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \
> + RISCV_ISA_EXT_ZVE64D, \
> + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +
> +static const unsigned int riscv_zve32f_exts[] = {
> + RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64f_exts[] = {
> + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64d_exts[] = {
> + RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64x_exts[] = {
> + RISCV_ISA_EXT_ZVE32X,
> + RISCV_ISA_EXT_ZVE64X
> +};
> +
> +static const unsigned int riscv_v_exts[] = {
> + RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
> /*
> * The canonical order of ISA extension names in the ISA string is defined in
> * chapter 27 of the unprivileged specification.
> @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
> __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
> __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> - __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> + __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
> __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
> __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
> __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> + __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
Hi Andy,
Nit: Since RISCV_ISA_EXT_ZVE32F is already used here as .id, you don't
need to insert it in the riscv_zve32f_exts array. It won't hurt but the
existing extensions that uses the __RISCV_ISA_EXT_SUPERSET() macro don't
do that.
> + __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> + __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> + __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> + __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
Ditto for the last 3 __RISCV_ISA_EXT_SUPERSET().
Apart from that, it looks good !
Thanks,
Clément
> __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
> __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
> __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
More information about the linux-riscv
mailing list