[PATCH v2] riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board

[Conor Dooley]

On Thu, Mar 07, 2024 at 08:21:12PM +0800, Shengyu Qu wrote:
> Interrupt line number of the AXP15060 PMIC is not a necessary part of
> its device tree. And this would cause kernel to try to enable interrupt
> line 0, which is not expected. So delete this part from device tree.
> 
> Cc: stable at vger.kernel.org
> Reported-by: Bo Gan <ganboing at gmail.com>
> Link: https://lore.kernel.org/all/c8b6e960-2459-130f-e4e4-7c9c2ebaa6d3@gmail.com/
> Signed-off-by: Shengyu Qu <wiagn233 at outlook.com>

Thanks for resending. Just to note that I already sent all 6.8 and 6.9
material, so since this is only something that manifests with that
"improved" version of OpenSBI I'm gonna pick this up after the merge
window.

Fixes: 2378341504de ("riscv: dts: starfive: Enable axp15060 pmic for cpufreq")

And hopefully I remember to re-write the commit message to mention that
the board doesn't actually connect the interrupt link to a GPIO etc, so
the original patch was invalid and a hack.

I should have rejected it and got the driver fixed at the time to allow
not having an interrupt, but clearly I didn't register that that zero
was a plic interrupt, not a GPIO.

Thanks,
Conor.

> ---
>  arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 45b58b6f3df8..7783d464d529 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -238,7 +238,6 @@ &i2c5 {
>  	axp15060: pmic at 36 {
>  		compatible = "x-powers,axp15060";
>  		reg = <0x36>;
> -		interrupts = <0>;
>  		interrupt-controller;
>  		#interrupt-cells = <1>;
>  
> -- 
> 2.39.2
> 
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