[PATCH v7 4/4] riscv: Set unaligned access speed at compile time

[Conor Dooley]

On Wed, Mar 06, 2024 at 12:00:04PM -0800, Charlie Jenkins wrote:
> +static u64 hwprobe_misaligned(const struct cpumask *cpus)
> +{
> +	if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS))
> +		if (unaligned_ctl_available())
> +			return RISCV_HWPROBE_MISALIGNED_EMULATED;
> +		else
> +			return RISCV_HWPROBE_MISALIGNED_SLOW;
> +	else if (IS_ENABLED(CONFIG_RISCV_SLOW_UNALIGNED_ACCESS))
> +		return RISCV_HWPROBE_MISALIGNED_SLOW;
> +	else if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS))
> +		return RISCV_HWPROBE_MISALIGNED_FAST;
> +}
> +#endif

Isn't this just
static u64 hwprobe_misaligned(const struct cpumask *cpus)
{
	if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS))
		return RISCV_HWPROBE_MISALIGNED_FAST;

	if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_available())
		return RISCV_HWPROBE_MISALIGNED_EMULATED;

	return RISCV_HWPROBE_MISALIGNED_SLOW;

}
?
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

The kconfig stuff looks ~good to me, I wanted to make one comment about
the wording of a sentence I wrote being pretty meh, but I think it's
time to let go there...


Cheers,
Conor.
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