[External] Re: [PATCH] RISC-V: Provide the frequency of mtime via hwprobe

[yunhui cui]

Hi Icenowy,

On Wed, Jun 19, 2024 at 7:51 AM Icenowy Zheng <uwu at icenowy.me> wrote:
>
> 在 2024-06-18星期二的 18:11 +0100，Jessica Clarke写道：
> > On 18 Jun 2024, at 12:46, Yunhui Cui <cuiyunhui at bytedance.com> wrote:
> > >
> > > From: Palmer Dabbelt <palmer at rivosinc.com>
> > >
> > > A handful of user-visible behavior is based on the frequency of the
> > > machine-mode time.
> > >
> > > Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
> > > Signed-off-by: Yunhui Cui <cuiyunhui at bytedance.com>
> >
> > I would suggest referring to the user-mode CSR instead, i.e. “time”
> > rather than “mtime” throughout in names and descriptions, since
> > that’s
> > the thing that user-mode software is actually reading from.
>
> Agree. MTIME isn't even a thing defined in RISC-V ISA -- it's part of
> the ACLINT timer spec, but before ACLINT gets widely accepted, it's
> just some SiFive thing that got copied by many other vendors (and
> vendors such as T-Head even provides CLINT w/o MTIME register (well
> because these T-Head cores have reference source code available, this
> is because of their CPU design uses an external counter fed as TIME
> register)).

Okay, Thanks for your suggestions,  I think this modification is more
appropriate:

RISC-V: Provide the frequency of time counter via hwprobe

A handful of user-visible behavior is based on the frequency of the
time counter.

What do you think ?

>
> >
> > Jess
> >
> >
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> > linux-riscv at lists.infradead.org
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>

Thanks,
Yunhui