[PATCH v16 0/5] riscv: sophgo: add clock support for sg2042
Conor Dooley
conor at kernel.org
Thu Jun 13 09:45:15 PDT 2024
On Thu, Jun 13, 2024 at 05:34:03PM +0800, Chen Wang wrote:
> ping ~~~
My suggestion is that you, as platform maintainer for sophgo, apply these
patches and send Stephen a pull request. That's usually the best way to
expedite patches for clock drivers.
Thanks,
Conor.
>
> On 2024/6/6 16:36, Chen Wang wrote:
> > From: Chen Wang <unicorn_wang at outlook.com>
> >
> > This series adds clock controller support for sophgo sg2042.
> >
> > Thanks,
> > Chen
> >
> > ---
> >
> > Changes in v16:
> >
> > The patch series is based on v6.10-rc1.
> >
> > Improved the dirvier code as per comments from Emil Renner Berthing.
> > - Split driver source file into three and change from built-in to module.
> > - Directly use status/enable pll register, no need to store them.
> > - Use FIELD_PREP/FIELD_GET to simplify the code.
> > - Some misc code improvements, such as for macro and local variables.
> >
> > Changes in v15:
> >
> > The patch series is based on v6.9-rc5. You can simply review or test the
> > patches at the link [16].
> >
> > Improved the dirvier code as per 3rd review comments from Stephen Boyd.
> > - Converted all parents described by strings to use clk_parent_data or
> > clk_hw directly.
> > - Just use struct clk_init_data::parent_hws when only have a clk_hw.
> > - Removed extra cleanup when use devm.
> > - Some misc code improvements.
> >
> > Changes in v14:
> >
> > The patch series is based on v6.9-rc1. You can simply review or test the
> > patches at the link [15].
> >
> > Improved the dirvier code as per 2nd review comments from Stephen Boyd.
> > - Inline the header file into source file.
> > - Use devm_xxx functions for pll/div/gate registeration.
> > - Use clk_parent_data for mux clocks initialization.
> > - Use u32 for registers readl/writel.
> > - Use devm_platform_ioremap_resource instead of devm_of_iomap.
> > - Cleanup some dead code and add definitions for some magic numbers.
> > - Add include files missed.
> > - Use kernel-doc to improve comments for some structure and functions.
> > - Other misc code cleanup work as per input from reviewers.
> >
> > Changes in v13:
> >
> > The patch series is based on v6.9-rc1. You can simply review or test the
> > patches at the link [14].
> >
> > Just added a minor fix for clk driver which was missed in v12.
> >
> > Changes in v12:
> >
> > The patch series is based on v6.9-rc1. You can simply review or test the
> > patches at the link [13].
> >
> > Improved the dirvier code as per review comments from Stephen Boyd.
> > - Remove default y for CLK_SOPHGO_SG2042.
> > - Optimize sg2042_pll_get_postdiv_1_2, move postdiv1_2 to the function.
> > scope and add more explaniation.
> > - Optimize sg2042_get_pll_ctl_setting.
> > - Switch to platform driver.
> > - Use clk_hw for initialization of struct clks.
> > - Don't use ignore_unused when using critical.
> > - Other code cleanup as per input form the reviewers.
> >
> > Changes in v11:
> >
> > The patch series is based on v6.8-rc5. You can simply review or test the
> > patches at the link [12].
> >
> > Quick fixed some dt_binding_check errors reported by Rob.
> >
> > Changes in v10:
> >
> > The patch series is based on v6.8-rc4. You can simply review or test the
> > patches at the link [11].
> >
> > Add input clocks for rpgate & clkgen.
> >
> > Changes in v9:
> > The patch series is based on v6.8-rc2. You can simply review or test the
> > patches at the link [10].
> >
> > From this version, drop the system-controller node due to there is no actual
> > device corresponding to it in IC design. SYS_CTRL is just a registers segment
> > defined on TRM for misc functions. Now three clock-controllers are defined for
> > SG2042, the control registers of the three clock-controllers are scattered in
> > different memory address spaces:
> > - the first one is for pll clocks;
> > - the second one is for gate clocks for RP subsystem;
> > - the third one is for div/mux, and gate clocks working for other subsystem
> > than RP subsystem.
> >
> > Changes in v8:
> > The patch series is based on v6.7. You can simply review or test the
> > patches at the link [9].
> > In this version, the main change is to split one clock provider into two.
> > Strictly follow the hardware instructions, in the memoymap, the control
> > registers of some clocks are defined in the SYS_CTRL segment, and the
> > control registers of other clocks are defined in the CLOCK segment.
> > Therefore, the new design defines two clock controllers, one as a child
> > node of the system control and the other as an independent clock controller
> > node.
> >
> > This modification involves a major modification to the binding files, so
> > the reviewed-by tags has been deleted.
> >
> > Changes in v7:
> > The patch series is based on v6.7. You can simply review or test the
> > patches at the link [8].
> > - fixed initval issue.
> > - fixed pll clk crash issue.
> > - fixed warning reported by <lkp at intel.com>
> > - code optimization as per review comments.
> > - code cleanup and style improvements as per review comments and checkpatch
> > with "--strict"
> >
> > Changes in v6:
> > The patch series is based on v6.7-rc1. You can simply review or test the
> > patches at the link [7].
> > - fixed some warnings/errors reported by kernel test robot <lkp at intel.com>.
> >
> > Changes in v5:
> > The patch series is based on v6.7-rc1. You can simply review or test the
> > patches at the link [6].
> > - dt-bindings: improved yaml, such as:
> > - add vendor prefix for system-ctrl property for clock generator.
> > - Add explanation for system-ctrl property.
> > - move sophgo,sg2042-clkgen.yaml to directly under clock folder.
> > - fixed bugs for driver Makefile/Kconfig
> > - continue cleaning-up debug print for driver code.
> >
> > Changes in v4:
> > The patch series is based on v6.7-rc1. You can simply review or test the
> > patches at the link [5].
> > - dt-bindings: fixed a dt_binding_check error.
> >
> > Changes in v3:
> > The patch series is based on v6.7-rc1. You can simply review or test the
> > patches at the link [3].
> > - DTS: don't use syscon but define sg2042 specific system control node. More
> > background info can read [4].
> > - Updating minor issues in dt-bindings as per input from reviews.
> >
> > Changes in v2:
> > The patch series is based on v6.7-rc1. You can simply review or test the
> > patches at the link [2].
> > - Squashed the patch adding clock definitions with the patch adding the
> > binding for the clock controller.
> > - Updating dt-binding for syscon, remove oneOf for property compatible;
> > define clock controller as child of syscon.
> > - DTS changes: merge sg2042-clock.dtsi into sg2042.dtsi; move clock-frequency
> > property of osc to board devicethree due to the oscillator is outside the
> > SoC.
> > - Fixed some bugs in driver code during testing, including removing warnings
> > for rv32_defconfig.
> > - Updated MAINTAINERS info.
> >
> > Changes in v1:
> > The patch series is based on v6.7-rc1. You can simply review or test the
> > patches at the link [1].
> >
> > Link: https://lore.kernel.org/linux-riscv/cover.1699879741.git.unicorn_wang@outlook.com/ [1]
> > Link: https://lore.kernel.org/linux-riscv/cover.1701044106.git.unicorn_wang@outlook.com/ [2]
> > Link: https://lore.kernel.org/linux-riscv/cover.1701691923.git.unicorn_wang@outlook.com/ [3]
> > Link: https://lore.kernel.org/linux-riscv/MA0P287MB03329AE180378E1A2E034374FE82A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM/ [4]
> > Link: https://lore.kernel.org/linux-riscv/cover.1701734442.git.unicorn_wang@outlook.com/ [5]
> > Link: https://lore.kernel.org/linux-riscv/cover.1701938395.git.unicorn_wang@outlook.com/ [6]
> > Link: https://lore.kernel.org/linux-riscv/cover.1701997033.git.unicorn_wang@outlook.com/ [7]
> > Link: https://lore.kernel.org/linux-riscv/cover.1704694903.git.unicorn_wang@outlook.com/ [8]
> > Link: https://lore.kernel.org/linux-riscv/cover.1705388518.git.unicorn_wang@outlook.com/ [9]
> > Link: https://lore.kernel.org/linux-riscv/cover.1706854074.git.unicorn_wang@outlook.com/ [10]
> > Link: https://lore.kernel.org/linux-riscv/cover.1708223519.git.unicorn_wang@outlook.com/ [11]
> > Link: https://lore.kernel.org/linux-riscv/cover.1708397315.git.unicorn_wang@outlook.com/ [12]
> > Link: https://lore.kernel.org/linux-riscv/cover.1711527932.git.unicorn_wang@outlook.com/ [13]
> > Link: https://lore.kernel.org/linux-riscv/cover.1711692169.git.unicorn_wang@outlook.com/ [14]
> > Link: https://lore.kernel.org/linux-riscv/cover.1713164546.git.unicorn_wang@outlook.com/ [15]
> > Link: https://lore.kernel.org/linux-riscv/cover.1714101547.git.unicorn_wang@outlook.com/ [16]
> >
> > ---
> >
> > Chen Wang (5):
> > dt-bindings: clock: sophgo: add pll clocks for SG2042
> > dt-bindings: clock: sophgo: add RP gate clocks for SG2042
> > dt-bindings: clock: sophgo: add clkgen for SG2042
> > clk: sophgo: Add SG2042 clock driver
> > riscv: dts: add clock generator for Sophgo SG2042 SoC
> >
> > .../bindings/clock/sophgo,sg2042-clkgen.yaml | 61 +
> > .../bindings/clock/sophgo,sg2042-pll.yaml | 53 +
> > .../bindings/clock/sophgo,sg2042-rpgate.yaml | 49 +
> > .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +
> > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 55 +-
> > drivers/clk/sophgo/Kconfig | 28 +
> > drivers/clk/sophgo/Makefile | 4 +
> > drivers/clk/sophgo/clk-sg2042-clkgen.c | 1152 +++++++++++++++++
> > drivers/clk/sophgo/clk-sg2042-pll.c | 570 ++++++++
> > drivers/clk/sophgo/clk-sg2042-rpgate.c | 291 +++++
> > drivers/clk/sophgo/clk-sg2042.h | 18 +
> > .../dt-bindings/clock/sophgo,sg2042-clkgen.h | 111 ++
> > include/dt-bindings/clock/sophgo,sg2042-pll.h | 14 +
> > .../dt-bindings/clock/sophgo,sg2042-rpgate.h | 58 +
> > 14 files changed, 2475 insertions(+), 1 deletion(-)
> > create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml
> > create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml
> > create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml
> > create mode 100644 drivers/clk/sophgo/clk-sg2042-clkgen.c
> > create mode 100644 drivers/clk/sophgo/clk-sg2042-pll.c
> > create mode 100644 drivers/clk/sophgo/clk-sg2042-rpgate.c
> > create mode 100644 drivers/clk/sophgo/clk-sg2042.h
> > create mode 100644 include/dt-bindings/clock/sophgo,sg2042-clkgen.h
> > create mode 100644 include/dt-bindings/clock/sophgo,sg2042-pll.h
> > create mode 100644 include/dt-bindings/clock/sophgo,sg2042-rpgate.h
> >
> >
> > base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
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