[PATCH v1 2/2] PCI: microchip: rework reg region handing

[Conor Dooley]

On Tue, Jun 11, 2024 at 12:10:54PM -0500, Bjorn Helgaas wrote:
> On Mon, May 27, 2024 at 10:37:17AM +0100, Conor Dooley wrote:
> > The PCI host controller on PolarFire SoC has multiple "instances", each
> > with their own bridge and ctrl address spaces. The original binding has
> > an "apb" register region, and it is expected to be set to the base
> > address of the host controllers register space. Defines in the driver
> > were used to compute the addresses of the bridge and ctrl address ranges
> > corresponding to instance1. Some customers want to use instance0 however
> > and that requires changing the defines in the driver, which is clearly
> > not a portable solution.
> > 
> > The binding has been changed from a single register region to a pair,
> > corresponding to the bridge and ctrl regions respectively, so modify the
> > driver to read these regions directly from the devicetree rather than
> > compute them from the base address of the abp region.
> > 
> > To maintain backwards compatibility with the existing binding, the
> > driver retains code to handle the "abp" reg and computes the base
> > address of the bridge and ctrl regions using the defines if it is
> > present. reg-names has always been a required property, so this is
> > safe to do.
> 
> When you update this, can you add something about the objective to the
> subject line?  "rework reg region handling" just says "we did
> something", but not why or what the benefit is.
> 
> The cover letter ("support using either instance 1 or 2") has good
> information that could be part of this.

Ye, sure.
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