[PATCH v1 5/5] riscv: dts: microchip: update pcie reg properties

[Conor Dooley]

Split the "apb" regions of memory on PolarFire SoC devicetrees PCIe
nodes into two regions, so that it will be possible to distinguish
between which root port instance is in use. Currently the "apb" region
points to the base of the root port region and the Linux driver uses
hard-coded offsets to find the "control" and "bridge" regions. The new
method for describing these regions explicitly passes the base address
for the two regions of interest.

Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 6 ++++--
 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi    | 6 ++++--
 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi | 6 ++++--
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 33e76db965bbc..f151aa2606d7b 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -45,8 +45,10 @@ pcie: pcie at 3000000000 {
 			#size-cells = <0x2>;
 			device_type = "pci";
 			dma-noncoherent;
-			reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
-			reg-names = "cfg", "apb";
+			reg = <0x30 0x0 0x0 0x8000000>,
+			      <0x0 0x43008000 0x0 0x00002000>,
+			      <0x0 0x4300a000 0x0 0x00002000>;
+			reg-names = "cfg", "bridge", "ctrl";
 			bus-range = <0x0 0x7f>;
 			interrupt-parent = <&plic>;
 			interrupts = <119>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
index 8230f06ddf48a..f5036126f2654 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
@@ -20,8 +20,10 @@ pcie: pcie at 2000000000 {
 		#interrupt-cells = <0x1>;
 		#size-cells = <0x2>;
 		device_type = "pci";
-		reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
-		reg-names = "cfg", "apb";
+		reg = <0x30 0x0 0x0 0x8000000>,
+		      <0x0 0x43008000 0x0 0x00002000>,
+		      <0x0 0x4300a000 0x0 0x00002000>;
+		reg-names = "cfg", "bridge", "ctrl";
 		bus-range = <0x0 0x7f>;
 		interrupt-parent = <&plic>;
 		interrupts = <119>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
index 9a56de7b91d64..121b13f9c8bf4 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -20,8 +20,10 @@ pcie: pcie at 2000000000 {
 		#interrupt-cells = <0x1>;
 		#size-cells = <0x2>;
 		device_type = "pci";
-		reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
-		reg-names = "cfg", "apb";
+		reg = <0x30 0x0 0x0 0x8000000>,
+		      <0x0 0x43008000 0x0 0x00002000>,
+		      <0x0 0x4300a000 0x0 0x00002000>;
+		reg-names = "cfg", "bridge", "ctrl";
 		bus-range = <0x0 0x7f>;
 		interrupt-parent = <&plic>;
 		interrupts = <119>;
-- 
2.43.2