[PATCH] RISC-V: fix vector insn load/store width mask

[Charlie Jenkins]

On Thu, Jun 06, 2024 at 02:28:00PM -0400, Jesse Taube wrote:
> RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
> Replace GENMASK(3, 0) with GENMASK(2, 0).
> 
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Jesse Taube <jesse at rivosinc.com>
> ---
>  arch/riscv/include/asm/insn.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index 06e439eeef9a..09fde95a5e8f 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -145,7 +145,7 @@
>  
>  /* parts of opcode for RVF, RVD and RVQ */
>  #define RVFDQ_FL_FS_WIDTH_OFF	12
> -#define RVFDQ_FL_FS_WIDTH_MASK	GENMASK(3, 0)
> +#define RVFDQ_FL_FS_WIDTH_MASK	GENMASK(2, 0)
>  #define RVFDQ_FL_FS_WIDTH_W	2
>  #define RVFDQ_FL_FS_WIDTH_D	3
>  #define RVFDQ_LS_FS_WIDTH_Q	4
> -- 
> 2.43.0
> 

Thanks!

Reviewed-by: Charlie Jenkins <charlie at rivosinc.com>