[PATCH 2/3] riscv: dts: starfive: jh7110: Add sys-syscon property to usbphy0

[Jan Kiszka]

From: Jan Kiszka <jan.kiszka at siemens.com>

Allows the PHY to connect to its USB controller.

Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com>
---
CC: Rob Herring <robh at kernel.org>
CC: Krzysztof Kozlowski <krzk+dt at kernel.org>
CC: Conor Dooley <conor+dt at kernel.org>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0d8339357bad..0c0b66a69065 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -606,6 +606,7 @@ usbphy0: phy at 10200000 {
 				 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
 			clock-names = "125m", "app_125m";
 			#phy-cells = <0>;
+			starfive,sys-syscon = <&sys_syscon 0x18>;
 		};
 
 		pciephy0: phy at 10210000 {
-- 
2.43.0