[PATCH v4 0/7] RISC-V: Detect and report speed of unaligned vector accesses

[Charlie Jenkins]

On Thu, Jul 11, 2024 at 05:58:39PM -0400, Jesse Taube wrote:
> Adds support for detecting and reporting the speed of unaligned vector
> accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
> adds Zicclsm to cpufeature and fixes the check for scalar unaligned
> emulated all CPUs. The vec_misaligned_speed key keeps the same format
> as the scalar unaligned access speed key.
> 
> This set does not emulate unaligned vector accesses on CPUs that do not
> support them. Only reports if userspace can run them and speed of
> unaligned vector accesses if supported.
> 
> If Zicclsm is present, the kernel will set both scalar and vector unaligned access speed to FAST.

Now that we have unfortunately realized that Zicclsm is not useful, this
patch no longer does this check, and doesn't use the Zicclsm bindings
in patch 1 and 2. This could be split out into a separate series, but
it's probably fine to leave the bindings in this series.

> 
> This patch requires the following patche to be applied first:
> RISC-V: fix vector insn load/store width mask
> https://lore.kernel.org/all/20240606182800.415831-1-jesse@rivosinc.com/
> 
> V1 -> V2:
>  - New patch: dt-bindings: riscv: Add Zicclsm ISA extension description.
>  - New patch: RISC-V: Check scalar unaligned access on all CPUs
>  - New patch: RISC-V: hwprobe: Document unaligned vector perf
> V2 -> V3:
>  - New patch: RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
>  - Split patch: RISC-V: Check scalar unaligned access on all CPUs
>  - New patch: RISC-V: Check Zicclsm to set unaligned access speed
> V3 -> V4:
>  - Drop patch: RISC-V: Check Zicclsm to set unaligned access speed
> 
> Jesse Taube (7):
>   RISC-V: Add Zicclsm to cpufeature and hwprobe
>   dt-bindings: riscv: Add Zicclsm ISA extension description.
>   RISC-V: Check scalar unaligned access on all CPUs
>   RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
>   RISC-V: Detect unaligned vector accesses supported
>   RISC-V: Report vector unaligned access speed hwprobe
>   RISC-V: hwprobe: Document unaligned vector perf key
> 
>  Documentation/arch/riscv/hwprobe.rst          |  21 +++
>  .../devicetree/bindings/riscv/extensions.yaml |   7 +
>  arch/riscv/Kconfig                            |  57 ++++++-
>  arch/riscv/include/asm/cpufeature.h           |   7 +-
>  arch/riscv/include/asm/entry-common.h         |  11 --
>  arch/riscv/include/asm/hwcap.h                |   1 +
>  arch/riscv/include/asm/hwprobe.h              |   2 +-
>  arch/riscv/include/asm/vector.h               |   1 +
>  arch/riscv/include/uapi/asm/hwprobe.h         |   6 +
>  arch/riscv/kernel/Makefile                    |   3 +-
>  arch/riscv/kernel/copy-unaligned.h            |   5 +
>  arch/riscv/kernel/cpufeature.c                |   1 +
>  arch/riscv/kernel/fpu.S                       |   4 +-
>  arch/riscv/kernel/sys_hwprobe.c               |  42 +++++
>  arch/riscv/kernel/traps_misaligned.c          | 134 ++++++++++++++--
>  arch/riscv/kernel/unaligned_access_speed.c    | 148 +++++++++++++++++-
>  arch/riscv/kernel/vec-copy-unaligned.S        |  58 +++++++
>  arch/riscv/kernel/vector.c                    |   2 +-
>  18 files changed, 472 insertions(+), 38 deletions(-)
>  create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S
> 
> -- 
> 2.45.2
>