[PATCH v4 4/4] membarrier: riscv: Provide core serializing command

[Mathieu Desnoyers]

On 2024-01-31 09:49, Andrea Parri wrote:
> RISC-V uses xRET instructions on return from interrupt and to go back
> to user-space; the xRET instruction is not core serializing.
> 
> Use FENCE.I for providing core serialization as follows:
> 
>   - by calling sync_core_before_usermode() on return from interrupt (cf.
>     ipi_sync_core()),
> 
>   - via switch_mm() and sync_core_before_usermode() (respectively, for
>     uthread->uthread and kthread->uthread transitions) before returning
>     to user-space.
> 
> On RISC-V, the serialization in switch_mm() is activated by resetting
> the icache_stale_mask of the mm at prepare_sync_core_cmd().
> 
> Suggested-by: Palmer Dabbelt <palmer at dabbelt.com>
> Signed-off-by: Andrea Parri <parri.andrea at gmail.com>

Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers at efficios.com>

-- 
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com