[PATCH 1/2] riscv: dts: sophgo: cv18xx: Add spi devices

[Conor Dooley]

On Mon, Jan 29, 2024 at 11:47:18AM +0800, Inochi Amaoto wrote:
> >Hi Inochi Amaoto
> >
> >On 10:26 Mon 29 Jan     , Inochi Amaoto wrote:
> >> Add spi devices for the CV180x, CV181x and SG200x soc.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> >> ---
> >>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 44 ++++++++++++++++++++++++++
> >>  1 file changed, 44 insertions(+)
> >>
> >> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >> index 7c88cbe8e91d..e66f9e9feb48 100644
> >> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >> @@ -176,6 +176,50 @@ uart3: serial at 4170000 {
> >>  			status = "disabled";
> >>  		};
> >>
> >> +		spi0: spi at 4180000 {
> >> +			compatible = "snps,dw-apb-ssi";
> >> +			reg = <0x04180000 0x10000>;
> >> +			interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> >> +			clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
> >> +			clock-names = "ssi_clk", "pclk";
> >..
> >> +			#address-cells = <1>;
> >> +			#size-cells = <0>;
> >I'd suggest moving those two above 'interrupts' property
> >
> >there is an ongoing discussion here..

Not super important to point out, but this discussion isn't "ongoing",
it was merged into 6.8-rc1:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html

Cheers,
Conor.

> >https://lore.kernel.org/all/20231203174622.18402-1-krzysztof.kozlowski@linaro.org/
> >
> 
> Thanks for this info. I will take care of it.
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