[PATCH v8 08/10] dt-bindings: riscv: Add Andes PMU extension description
Yu Chien Peter Lin
peterlin at andestech.com
Mon Jan 29 01:25:51 PST 2024
Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.
Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Acked-by: Conor Dooley <conor.dooley at microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
Changes v2 -> v3:
- New patch
Changes v3 -> v4:
- Include Conor's Acked-by
Changes v4 -> v5:
- Include Prabhakar's Reviewed-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 63d81dc895e5..468c646247aa 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,5 +477,12 @@ properties:
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: xandespmu
+ description:
+ The Andes Technology performance monitor extension for counter overflow
+ and privilege mode filtering. For more details, see Counter Related
+ Registers in the AX45MP datasheet.
+ https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
additionalProperties: true
...
--
2.34.1
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